Alternatives and similar repositories for RTL-Coding

Users that are interested in RTL-Coding are comparing it to the libraries listed below

• Ummidichandrika / 100-Days-of-RTL
  ☆113Updated last year
• Artityagi123456789 / 100DaysofRTL
  ☆17Updated last year
• karribharathi / 100-Days-of-RTL
  ☆16Updated last year
• KOTHAVANI / 100-Days-of-RTL-code
  ☆41Updated last year
• Artityagi123456789 / -100dasofSystemVerilog
  System Verilog using Functional Verification
  ☆12Updated last year
• ChinnuReddySeelam / 100DaysRTL_Part1_HDL
  ☆10Updated last year
• rpjayaraman / DV-resource
  A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.
  ☆19Updated last month
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆31Updated 5 years ago
• JAYRAM711 / 100-DAYS-OF-RTL
  This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…
  ☆19Updated last year
• bpvsr / 2_Interview_Questions
  # 3.Interview_Questions In my experience, the questions i faced in the interviews and the people surrounded me must have faced a couple o…
  ☆22Updated last week
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆92Updated 2 years ago
• Abhishek-Sharma182005 / 108-RTL-Projects
  Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…
  ☆17Updated 5 months ago
• Prananya123 / RTL-Coding
  ☆22Updated 2 years ago
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆33Updated last year
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆17Updated last year
• Kholoud-Ebrahim / SPI_Protocol
  UVM based Verification of SPI_Protocol. A Serial intra System Communication Peripheral Protocol.
  ☆8Updated last year
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆83Updated 2 years ago
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆152Updated 10 months ago
• naragece / uvm-testbench-tutorial-simple-adder
  A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology
  ☆105Updated 11 years ago
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆383Updated 11 months ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆62Updated 2 years ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆151Updated 5 years ago
• muneebullashariff / best_coding_practices
  Describes the best coding practices and guidelines
  ☆11Updated last year
• shubhi704 / APB-Protocol
  ☆46Updated 4 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆127Updated 4 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆105Updated 6 months ago
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆24Updated last year
• OrsuVenkataKrishnaiah1235 / RTL-Coding
  "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
  ☆14Updated last year
• ashok-g-r / 100-Days-of-RTL
  ☆16Updated 2 years ago
• smartfoxdata / axi4lite_gpio
  General purpose IO port with AXI4-Lite interface
  ☆10Updated 5 months ago