preusser / q27Links
27-Queens Puzzle: Massively Parellel Enumeration and Solution Counting
☆85Updated 7 years ago
Alternatives and similar repositories for q27
Users that are interested in q27 are comparing it to the libraries listed below
Sorting:
- C++ truth table library☆56Updated last month
- An advanced header-only exact synthesis library☆26Updated 2 years ago
- A circuit toolkit☆102Updated 5 years ago
- The Pseudo-Boolean Solver MiniSat+☆27Updated 12 years ago
- Lingeling SAT Solver☆102Updated last year
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆92Updated last year
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 4 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- firrtlator is a FIRRTL C++ library☆21Updated 8 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆101Updated 5 years ago
- Block-diagram style digital logic visualizer☆23Updated 9 years ago
- A SAT solver implementation in VHDL, team tussle☆20Updated 9 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- The BERI and CHERI processor and hardware platform☆49Updated 8 years ago
- The probSAT SAT Solver☆22Updated 2 years ago
- FPGA synthesis tool powered by program synthesis☆49Updated last month
- Chisel/Firrtl execution engine☆153Updated 10 months ago
- A Hardware Pipeline Description Language☆45Updated last year
- ☆11Updated 3 years ago
- AIGER And-Inverter-Graph Library☆79Updated 3 weeks ago
- Library to plot integer sets and maps☆49Updated 8 years ago
- CNF generator in DIMACS format. It produces common families of CNFs.☆68Updated last month
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 4 years ago
- C++ parsing library for simple formats used in logic synthesis and formal verification☆36Updated last year
- A modern (2017) compilable re-host of the Espresso heuristic logic minimizer.☆151Updated 5 years ago
- A Parallel SAT Solver with GPU Accelerated Inprocessing☆118Updated 2 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆142Updated last month
- The Standard Interface for Incremental Satisfiability Solving☆49Updated 3 years ago
- A fault-injection framework using Chisel and FIRRTL☆36Updated last month
- Time-sensitive affine types for predictable hardware generation☆143Updated 11 months ago