muhos / ParaFROST
A Parallel SAT Solver with GPU Accelerated Inprocessing
☆86Updated last month
Related projects ⓘ
Alternatives and complementary repositories for ParaFROST
- ☆47Updated 6 months ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆25Updated 3 months ago
- Structured BVA☆30Updated 6 months ago
- The glucose SAT solver☆77Updated this week
- A generic parser and tool package for the BTOR2 format.☆40Updated 2 months ago
- Pono: A flexible and extensible SMT-based model checker☆80Updated 2 weeks ago
- AIGER And-Inverter-Graph Library☆61Updated 5 months ago
- Multi-core Decision Diagram (BDD/LDD) implementation☆41Updated 11 months ago
- Reads a state transition system and performs property checking☆76Updated this week
- BTOR2 MLIR project☆16Updated 9 months ago
- Cube-and-Conquer SAT solver☆31Updated last year
- A translation validation framework for MLIR☆73Updated 2 weeks ago
- SMTSampler: Efficient Stimulus Generation from Complex SMT Constraints☆24Updated 5 years ago
- AMulet 2. - A better AIG Multiplier Examination Tool☆20Updated 2 years ago
- A high-performance implementation of the IC3/PDR algorithm in Rust.☆14Updated this week
- IC3 reference implementation: a short, simple, fairly competitive implementation of IC3. Read it, tune it, extend it, play with it.☆55Updated 9 years ago
- A generic C++ API for SMT solving. It provides abstract classes which can be implemented by different SMT solvers.☆114Updated this week
- Parallel SAT solver that won the SAT Competition 2022 by a large margin (24% faster than the 2nd ranked solver)☆20Updated last year
- C++ truth table library☆50Updated 7 months ago
- py-aiger: A python library for manipulating sequential and combinatorial circuits encoded using `and` & `inverter` gates (AIGs).☆41Updated 7 months ago
- SAT Solver SATCH☆107Updated 2 years ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆60Updated this week
- ☆32Updated 3 months ago
- An I/O-efficient implementation of (Binary) Decision Diagrams☆24Updated 2 weeks ago
- FPGA synthesis tool powered by program synthesis☆38Updated last month
- CoreIR Symbolic Analyzer☆61Updated 4 years ago
- Approximate Model Counter☆70Updated 3 months ago
- A simple SAT solver based on the CDCL algorithm☆18Updated 5 years ago
- A pure, low-level tensor program representation enabling tensor program optimization via program rewriting. See the web demo at https://g…☆71Updated 5 months ago
- A fast and certifying solver for quantified Boolean formulas.☆26Updated 6 months ago