lnis-uofu / JPEG_LS
☆19Updated last year
Related projects ⓘ
Alternatives and complementary repositories for JPEG_LS
- An FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器,用来进行无损图像压缩。☆89Updated 2 months ago
- An FPGA-based high performance MPEG2 encoder for video compression. 基于FPGA的高性能MPEG2视频编码器,可实现视频压缩。☆116Updated 9 months ago
- A lightweight image converter which supports PNG, PNM, BMP, QOI, JPEG-LS, and H.265 intra-frame.☆46Updated last month
- Bitmap Processing Library & AXI-Stream Video Image VIP☆29Updated 2 years ago
- An FPGA-based GZIP (deflate) compressor, which input raw data and output standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压…☆100Updated last year
- AXI协议规范中文翻译版☆132Updated 2 years ago
- An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码…☆211Updated 2 months ago
- ☆63Updated 2 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆107Updated 2 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆46Updated 4 years ago
- ☆34Updated 9 years ago
- AHB DMA 32 / 64 bits☆50Updated 10 years ago
- H264视频解码verilog实现☆78Updated 7 years ago
- image processing based FPGA☆98Updated 3 years ago
- Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…☆141Updated last year
- Step by step tutorial for building CortexM0 SoC☆35Updated 2 years ago
- JPEG Encoder Verilog☆71Updated 2 years ago
- An FPGA-based LZMA compressor for generic data compression. 基于FPGA的LZMA压缩器,用于通用数据压缩。☆74Updated last year
- 视频旋转(2019FPGA大赛)☆29Updated 4 years ago
- AXI总线连接器☆91Updated 4 years ago
- A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器,用来读写硬盘。☆85Updated last year
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆21Updated last year
- FPGA图像处理仿真平台☆25Updated 2 years ago
- AXI DMA 32 / 64 bits☆100Updated 10 years ago
- Constrast limited adaptive histogram equlization based on Verilog☆26Updated last year
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆111Updated 3 years ago
- ☆51Updated last year
- APB to I2C☆40Updated 10 years ago
- Cortex M0 based SoC☆70Updated 3 years ago
- An FPGA-based AXI4 DDR1 controller. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。☆147Updated last year