lnis-uofu / JPEG_LS
☆19Updated last year
Related projects: ⓘ
- A light-weight JPEG-LS (ITU-T T.87) image encoder. 仅400行C语言的JPEG-LS图像编码器。☆38Updated 2 weeks ago
- FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器,用来进行无损图像压缩。☆84Updated this week
- FPGA-based high performance MPEG2 encoder for video compression. 基于FPGA的高性能MPEG2视频编码器,可实现视频压缩。☆108Updated 7 months ago
- FPGA-based GZIP (deflate) compressor. Input raw data and output standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压缩器。输入原始数据…☆92Updated last year
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆104Updated 2 years ago
- An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码…☆199Updated this week
- FPGA-based LZMA compressor for generic data compression. 基于FPGA的LZMA压缩器,用于通用数据压缩。☆69Updated last year
- A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器,用来读写硬盘。☆80Updated last year
- 使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例☆85Updated this week
- JPEG Encoder Verilog☆67Updated last year
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆20Updated last year
- NBLIC is a lossless grayscale image compression algorithm with high compression ratio. 一种高压缩率的灰度图像压缩格式。☆31Updated last month
- Bitmap Processing Library & AXI-Stream Video Image VIP☆27Updated 2 years ago
- A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库,提供算术运算、…☆122Updated last year
- image processing based FPGA☆94Updated 3 years ago
- Verilog implementation of SHA1/SHA224/SHA256/SHA384/SHA512. 使用Verilog实现的SHA1/SHA224/SHA256/SHA384/SHA512计算器。☆59Updated last year
- Bilinear interpolation realizes image scaling based on FPGA☆18Updated 4 years ago
- ☆61Updated last year
- A simple JPEG2000 hardware encoder☆15Updated 3 years ago
- Include 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调试器。☆102Updated last year
- AXI协议规范中文翻译版☆124Updated 2 years ago
- H264视频解码verilog实现☆75Updated 7 years ago
- An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。☆134Updated last year
- CNN accelerator implemented with Spinal HDL☆128Updated 7 months ago
- SDRAM controller with AXI4 interface☆75Updated 5 years ago
- AHB DMA 32 / 64 bits☆48Updated 10 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆37Updated 4 years ago
- An FPGA-based PNG image decoder, which can extract original pixels from PNG files. 基于FPGA的PNG图像解码器,可以从PNG文件中解码出原始像素。☆85Updated last year
- ☆49Updated last year
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆46Updated last year