Alternatives and similar repositories for AArch64-Explore

Users that are interested in AArch64-Explore are comparing it to the libraries listed below

• Veedrac / microarchitecturometer
  Measures microarchitectural details such as ROB size. Like https://github.com/travisdowns/robsize but without runtime code generation, wh…
  ☆130Updated 4 years ago
• dougallj / applecpu
  Apple Firestorm/Icestorm CPU microarchitecture docs
  ☆241Updated 2 years ago
• travisdowns / robsize
  ROB size testing utility
  ☆157Updated 3 years ago
• junjie1475 / MacOS_CoreBinder
  Kernel Extension allows to pin thread on a certain cpu core on Apple Silicon machines
  ☆19Updated 9 months ago
• ChipsandCheese / Microbenchmarks
  Trying to figure various CPU things out
  ☆86Updated last year
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆127Updated this week
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆157Updated 3 years ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆176Updated 3 weeks ago
• riscv-non-isa / rvv-intrinsic-doc
  ☆345Updated last week
• lowRISC / riscv-llvm
  RISC-V support for LLVM projects (LLVM, Clang, ...)
  ☆273Updated last year
• shioyadan / Konata
  Konata is an instruction pipeline visualizer for Onikiri2-Kanata/Gem5-O3PipeView formats. You can download the pre-built binaries from ht…
  ☆478Updated last year
• ocxtal / insn_bench_aarch64
  Instruction latency & throughput profiler for AArch64
  ☆39Updated 3 weeks ago
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆152Updated last week
• toddmaustin / bringup-bench
  Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, …
  ☆194Updated 2 weeks ago
• ccelio / Speckle
  A wrapper for the SPEC CPU2006 benchmark suite.
  ☆89Updated 4 years ago
• gthparch / macsim
  A heterogeneous architecture timing model simulator.
  ☆165Updated this week
• herd / herdtools7
  The Herd toolsuite to deal with .cat memory models (version 7.xx)
  ☆268Updated this week
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆187Updated last week
• sparcians / map
  Modeling Architectural Platform
  ☆202Updated 3 weeks ago
• dougallj / applegpu
  Apple G13 GPU architecture docs and tools
  ☆616Updated 4 months ago
• ucb-bar / berkeley-softfloat-3
  SoftFloat release 3
  ☆295Updated 6 months ago
• clamchowder / Microbenchmarks
  Trying to figure various CPU things out
  ☆143Updated 2 months ago
• riscv / riscv-profiles
  RISC-V Architecture Profiles
  ☆166Updated last week
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆121Updated 9 months ago
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆61Updated 2 months ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆89Updated 3 months ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆129Updated this week
• comsec-group / cascade-artifacts
  Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)
  ☆133Updated last year
• umd-memsys / DRAMSim2
  DRAMSim2: A cycle accurate DRAM simulator
  ☆279Updated 4 years ago
• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆191Updated 2 weeks ago