Alternatives and similar repositories for biodivine-lib-bdd

Users that are interested in biodivine-lib-bdd are comparing it to the libraries listed below

• OxiDD / oxidd
  Concurrent decision diagram framework written in Rust
  ☆64Updated last month
• viperproject / mendel-verifier
  Capability-based verifier for safe Rust clients of interior mutability
  ☆13Updated last year
• jix / flussab
  Collection of utlities for writing parsers. Includes a fast DIMACS CNF parser.
  ☆14Updated 10 months ago
• stanford-centaur / pono
  Pono: A flexible and extensible SMT-based model checker
  ☆110Updated this week
• uwplse / ruler
  Rewrite Rule Inference Using Equality Saturation
  ☆136Updated 3 months ago
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆66Updated 2 weeks ago
• flyvy-verifier / flyvy
  An experimental framework for temporal verification based on first-order linear-time temporal logic. Our goal is to express transition sy…
  ☆18Updated 2 weeks ago
• jetafese / btor2mlir
  Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification
  ☆15Updated 2 weeks ago
• gipsyh / rIC3-HWMCC24
  rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission
  ☆12Updated 2 months ago
• jix / varisat
  SAT solver written in Rust
  ☆272Updated 2 years ago
• jix / kissat_extras
  A fork of the Kissat SAT solver with additional features. Supports incremental solving.
  ☆15Updated 3 years ago
• mikeurbach / egg-netlist-synthesizer
  Using e-graphs to synthesize netlists from boolean logic.
  ☆14Updated 2 years ago
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated last year
• shnarazk / splr
  A modern (trail saving, clause subsumption/vivification, learning-rate based selecting, rephrase) CDCL SAT solver in Rust
  ☆99Updated 2 months ago
• CoriolisSP / FuzzBtor2
  Random Generator of Btor2 Files
  ☆10Updated 2 years ago
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆10Updated 11 months ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆83Updated this week
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆56Updated this week
• ssoelvsten / bdd-benchmark
  Benchmarking Suite for BDD packages
  ☆17Updated this week
• calyxir / calyx-riscv
  RISCV Core written in Calyx
  ☆17Updated last year
• BurtonQin / Awesome-Rust-Checker
  A curated list of awesome Rust checkers
  ☆49Updated 5 months ago
• hwmcc / btor2tools
  A generic parser and tool package for the BTOR2 format.
  ☆42Updated this week
• hopv / rust-horn
  RustHorn: A CHC-based automated verifier for Rust
  ☆86Updated 6 months ago
• sgpthomas / comp-gen
  Automatically generate a compiler using equality saturation
  ☆30Updated last year
• IntelLabs / pycaliper
  PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…
  ☆22Updated 3 months ago
• d-kfmnn / amulet2
  AMulet 2. - A better AIG Multiplier Examination Tool
  ☆26Updated 2 years ago
• rems-project / isla
  Symbolic execution tool for Sail ISA specifications
  ☆78Updated last week
• ssoelvsten / adiar
  An I/O-efficient implementation of (Binary) Decision Diagrams
  ☆29Updated this week
• microsoft / verus-proof-synthesis
  ☆46Updated 3 weeks ago
• aman-goel / avr
  Reads a state transition system and performs property checking
  ☆87Updated last week