leleonardzhang / CapuchinLinks
A framework and model generator for Neural Network inferences on MSP430
☆11Updated 3 years ago
Alternatives and similar repositories for Capuchin
Users that are interested in Capuchin are comparing it to the libraries listed below
Sorting:
- Release repo for SONIC and TAILS☆20Updated 4 years ago
- MLPerf™ Tiny is an ML benchmark suite for extremely low-power systems such as microcontrollers☆410Updated this week
- ☆229Updated 2 years ago
- ☆10Updated 7 years ago
- HLS based Deep Neural Network Accelerator Library for Xilinx Ultrascale+ MPSoCs☆325Updated 5 years ago
- ☆9Updated 5 years ago
- Explore the energy-efficient dataflow scheduling for neural networks.☆222Updated 4 years ago
- Repository to host and maintain scale-sim-v2 code☆300Updated last month
- DPU on PYNQ☆221Updated last year
- generate tflite micro code which bypasses the interpreter (directly calls into kernels)☆80Updated 2 years ago
- Vitis HLS Library for FINN☆198Updated this week
- SDSoC™ (Software-Defined System-On-Chip) Environment Tutorials☆154Updated 5 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆138Updated last week
- PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.☆200Updated 2 years ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆143Updated this week
- An analytical cost model evaluating DNN mappings (dataflows and tiling).☆217Updated last year
- μNAS is a neural architecture search (NAS) system that designs small-yet-powerful microcontroller-compatible neural networks.☆80Updated 4 years ago
- ☆351Updated 2 years ago
- CMSIS-NN Library☆277Updated this week
- Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrol…☆503Updated 2 months ago
- Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.☆216Updated 6 years ago
- ☆431Updated 8 months ago
- End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.☆237Updated 2 years ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆345Updated 4 months ago
- Fast and accurate DRAM power and energy estimation tool☆163Updated 2 weeks ago
- Tool for optimize CNN blocking☆94Updated 5 years ago
- MLPerf (tm) Tiny Deep Learning Benchmarks for STM32 devices☆13Updated last year
- Ares: A framework for quantifying the resilience of deep neural networks☆36Updated 5 years ago
- Dataflow QNN inference accelerator examples on FPGAs☆217Updated 2 months ago
- FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)☆272Updated 5 years ago