LEVEL: Open-source RV32IMC RISC-V processor core with pipelined microarchitecture, cache support, SoC peripherals and verification framework.
☆34Jul 6, 2026Updated 3 months ago
Alternatives and similar repositories for level-v
Users that are interested in level-v are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆22Sep 30, 2026Updated last month
- ☆25Apr 24, 2026Updated 6 months ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- A progressive course in digital design and verification covering UART, SPI, and I²C — from specification and RTL through UVM-based verifi…☆20May 30, 2026Updated 5 months ago
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆36Nov 1, 2025Updated 11 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This is full tutorial of UVM (Universal Verification Methodology) for a simple ALU unit☆29Jul 27, 2018Updated 8 years ago
- open source hardware synthesis. SystemVerilog, VHDL and ABEL-HDL to gate-level netlists☆45Aug 25, 2026Updated 2 months ago
- Open-source Neural Processing Unit (NPU) from China ❤☆55Jan 29, 2025Updated last year
- Test dashboard for verification features in Verilator☆35Updated this week
- UVM Testbench for a SRAM☆14Dec 18, 2020Updated 5 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 7 years ago
- Portable four-parameter vital signs monitor (ECG, SpO2, temperature, respiration) built on ESP32. Biomedical engineering bachelor's proje…☆18Jul 9, 2026Updated 3 months ago
- WaveEye is an AXI4-Lite protocol root cause analysis tool that explains why a violation must occur by identifying missing inter-FSM depen…☆13Mar 30, 2026Updated 7 months ago
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆29Jan 6, 2026Updated 9 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- This document is a project of cmos image sensor system. The doc mainly includes LUPA4000 Cmos sensor driving, SDRAM storage, LVDS data re…☆13Feb 7, 2021Updated 5 years ago
- List of several designs I have been working through the years to avoid re-designing it again☆16Jun 17, 2024Updated 2 years ago
- ☆14Jun 9, 2026Updated 4 months ago
- DPI module for UART-based console interaction with Verilator simulations☆28Oct 27, 2012Updated 14 years ago
- This is a TCL script that will take in Verilog and VHDL files and generate an instantiation template appropriately for the user to use in…☆10Dec 19, 2012Updated 13 years ago
- RISCV Gem5 simulator flow for Architetture dei Sistemi di Elaborazione☆38Updated this week
- A complete UVM verification testbench for FIFO☆14Mar 21, 2016Updated 10 years ago
- Formal Verification of RISC V IM Processor☆12Mar 27, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Source-available SystemVerilog RTL for a custom FPGA Ethernet datapath with ARP, IPv4, UDP, and specialized TCP transport control.☆42Jul 30, 2026Updated 3 months ago
- ☆27May 31, 2021Updated 5 years ago
- Pequeno R5 (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32IM ISA.☆161Aug 21, 2026Updated 2 months ago
- Bu depo TEKNOFEST 2023 Çip Tasarım Yarışması'nda Analog Tasarım ve Sayısal İşlemci Tasarımı kategorilerinde çeşitli dosyaları paylaşmak i…☆24Apr 13, 2023Updated 3 years ago
- Open-source SystemVerilog simulator in Rust. 4-state, event-driven, IEEE 1800-2023, runs real UVM.☆120Updated this week
- An Affective Platform for AI in an Interdisciplinary Setting☆12May 25, 2026Updated 5 months ago
- This repository implements a scaled-down LLaMA 2-like model on an ARM Cortex-M3 soft core, with a custom systolic array RTL module for ef…☆16Jun 25, 2025Updated last year
- PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities☆155Jun 16, 2026Updated 4 months ago
- Dual-Core Out-of-Order MIPS CPU Design☆26May 8, 2025Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Kasırga - Gök Sayısal İşlemci Kategorisi RISC-V İşlemci Tasarımı☆20May 27, 2023Updated 3 years ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆14Sep 28, 2022Updated 4 years ago
- Wishbone controlled I2C controllers☆63Aug 10, 2026Updated 2 months ago
- A Constant False Alarm Rate Processor Generator☆11Apr 13, 2023Updated 3 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆139Dec 17, 2023Updated 2 years ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆37Mar 23, 2024Updated 2 years ago
- BlackParrot on Zynq☆56Jun 17, 2026Updated 4 months ago