Awesome List of my own!
☆113Sep 23, 2025Updated 9 months ago
Alternatives and similar repositories for awesome-stars
Users that are interested in awesome-stars are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- CPU micro benchmarks☆83Jun 19, 2026Updated last week
- 基于龙芯FPGA开发板的计算机综合系统实验☆26Dec 16, 2018Updated 7 years ago
- A hand-written recursive decent Verilog parser.☆10Updated this week
- Warning: 🕳 ahead!☆16Jan 8, 2020Updated 6 years ago
- Project template for Artix-7 based Thinpad board☆52Sep 13, 2025Updated 9 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Gem5 with PCI Express integrated.☆24Sep 29, 2018Updated 7 years ago
- The official repository for the gem5 computer-system architecture simulator.☆15May 12, 2026Updated last month
- Computer System Project for Loongson FPGA Board in 2017☆54Jun 3, 2018Updated 8 years ago
- The cold linker☆73May 7, 2026Updated last month
- A simple USB to UART board designed with KiCad.☆14May 4, 2023Updated 3 years ago
- PKU CompNet'19 Lab 2 - Homebrew TCP☆12Nov 29, 2019Updated 6 years ago
- My knowledge base☆99Updated this week
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated 2 years ago
- HERMES: sHallow dirEctory stRucture Many-filE fileSystem☆20Jun 9, 2019Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)☆14Oct 8, 2020Updated 5 years ago
- Relaxed Rust (for cats)☆14Nov 20, 2019Updated 6 years ago
- Modular, flexible, cross-platform workload profiling and characterization☆13Mar 1, 2021Updated 5 years ago
- Simulator of a memory controller to connect DRAMSim and FlashDIMMSim into one unified memory☆17Apr 4, 2024Updated 2 years ago
- Generate graphviz dot files from InfiniBand topology dumps.☆17Feb 11, 2024Updated 2 years ago
- RV32I by cats☆15Sep 4, 2023Updated 2 years ago
- Lab for Network Principles since 2019-2020 fall☆176Sep 22, 2025Updated 9 months ago
- 基于FPGA实现用户态中断硬件机制与优化操作系统内核☆10Apr 1, 2025Updated last year
- THU compiler principle course homework, written in rust. (this is not the pa framework)☆13Dec 24, 2018Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Naïve MIPS32 SoC implementation☆117Jun 23, 2020Updated 6 years ago
- Documentation for Router Lab☆73May 20, 2026Updated last month
- ☆23Apr 24, 2026Updated 2 months ago
- Run SPEC CPU 2017 benchmark on OpenHarmony/HarmonyOS NEXT☆38Jun 18, 2025Updated last year
- A Rust style C++ library.☆19Sep 3, 2022Updated 3 years ago
- 计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位☆127Dec 4, 2025Updated 6 months ago
- Fast TLB simulator for RISC-V systems☆16May 16, 2019Updated 7 years ago
- GNU libiconv with UTF-8-MAC support and fixes (Port from Apple's GNU libiconv)☆18Feb 25, 2025Updated last year
- This is a Project to Integrate and Automate the functions of three tools named gem5, McPAT and HotSpot.☆11Jul 1, 2019Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Microbenchmarking experiments on Zen 2 machines☆22Jun 25, 2022Updated 4 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- Alloy models for automatic synthesis of memory model litmus test suites (from ASPLOS 2017)☆16Jan 26, 2024Updated 2 years ago
- Zero-Config Single-Node Workload Manager☆17Jan 5, 2021Updated 5 years ago
- Wallace and Dadda tree multiplier generator in vhdl and verilog☆14Mar 14, 2026Updated 3 months ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆21Updated this week
- Reduced on-disk Suffix Array☆22Oct 9, 2013Updated 12 years ago