Claude Code / Codex CLI skill that scaffolds a runnable UVM testbench (APB / AHB-Lite / AXI4-Lite + generic-bus fallback) from an IP spec and register table, with a UVM-sequence flow for DV and a tb_api:: task BFM for DE.
☆27Jul 14, 2026Updated 3 months ago
Alternatives and similar repositories for gen-tb-skill
Users that are interested in gen-tb-skill are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Open-source, evidence-driven MCP server for RTL simulation debugging: correlate VCS/Xcelium logs, VCD/FSDB waveforms, SystemVerilog/UVM s…☆119Oct 13, 2026Updated last week
- xverif is a local toolkit for chip-verification debug agents. It contains deterministic tools for design and waveform debug, coverage, bi…☆109Oct 10, 2026Updated last week
- ☆63May 22, 2026Updated 5 months ago
- Open-source, agent-agnostic RTL formal verification skill library for AI coding agents: JasperGold FPV, SVA, proof optimization, and TCL …☆34Sep 29, 2026Updated 3 weeks ago
- ☆25Mar 19, 2026Updated 7 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Extending BookSim2.0 and HotSpot6.0 for Power, Performance and Thermal evaluation of 3D NoC Architectures☆14Aug 9, 2019Updated 7 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆11Oct 3, 2017Updated 9 years ago
- Systemverilog DPI-C call Python function☆29Mar 11, 2021Updated 5 years ago
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 13 years ago
- A python project to automatically generate the UVM testbench document.☆21Feb 27, 2024Updated 2 years ago
- VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a sta…☆55Oct 5, 2026Updated 2 weeks ago
- svlib from http://www.verilab.com/resources/svlib/☆28Jun 2, 2020Updated 6 years ago
- YAMM package repository☆35Mar 20, 2023Updated 3 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆37Apr 15, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- some gnu radio demo for antsdr☆19Nov 25, 2021Updated 4 years ago
- Serpens is an HBM FPGA accelerator for SpMV☆23Jul 26, 2024Updated 2 years ago
- Syntacore first stage bootloader☆11Jan 19, 2026Updated 9 months ago
- Course content for the University of Bristol Design Verification course.☆68Oct 1, 2026Updated 3 weeks ago
- OpenExSys_NoC a mesh-based network on chip IP.☆21Dec 1, 2023Updated 2 years ago
- AI-Powered Hardware Design & Verification Copilot - Plugin for your CLI☆23Jul 12, 2026Updated 3 months ago
- UVM interactive debug library☆36Feb 28, 2026Updated 7 months ago
- ☆12Sep 1, 2021Updated 5 years ago
- This repository defines a Claude Code skill for working with Verilog☆19Apr 21, 2026Updated 6 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆26Mar 25, 2025Updated last year
- UCAS SEP扩展脚本 - 课程评估辅助 etc.☆13Apr 3, 2025Updated last year
- Parse FSDB waveform files☆24Apr 13, 2026Updated 6 months ago
- (Not actively updating)Vision Transformer Accelerator implemented in Vivado HLS for Xilinx FPGAs.☆26Dec 29, 2024Updated last year
- EpicSim Project☆71Mar 1, 2021Updated 5 years ago
- This is a uvm example. The video is available at https://www.bilibili.com/video/BV1yq4y177f6/☆52Mar 2, 2022Updated 4 years ago
- ☆21Jan 13, 2026Updated 9 months ago
- Digital HDL Design Full-stack Agents☆221Updated this week
- 非雇员OD管理复盘与面试改进思考☆16Jul 2, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Agent skills for veriloga☆35Jul 21, 2026Updated 3 months ago
- NetCracker is an FPGA architecture analysis tool for facilitating the investigation of connectivity patterns within as well as in between…☆19Dec 4, 2020Updated 5 years ago
- Standalone application based on ADI hdl and no_OS for ANTSDR.☆30Mar 27, 2025Updated last year
- ☆54Jan 9, 2026Updated 9 months ago
- generate UVM testbench using python☆28Mar 24, 2018Updated 8 years ago
- VCML integration of Nvidia's NVDLA SystemC model☆14Apr 13, 2021Updated 5 years ago
- A Material 3 Music Player with YouTube Music support for Android. Forked from InnerTune☆17Updated this week