Claude Code / Codex CLI skill that scaffolds a runnable UVM testbench (APB / AHB-Lite / AXI4-Lite + generic-bus fallback) from an IP spec and register table, with a UVM-sequence flow for DV and a tb_api:: task BFM for DE. | 基于 IP 规格书与寄存器表一键生成可运行的 UVM 验证环境,内建 APB / AHB-Lite / AXI4-Lite,其它单通道总线走 generic 回退,同时为 DV 提供 UVM 序列接口、为 DE 提供 tb_api::…
☆21Jul 14, 2026Updated last month
Alternatives and similar repositories for gen-tb-skill
Users that are interested in gen-tb-skill are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 简洁的测试平台日志，波形(FSDB/VCD)，根因分析MCP Server. A Simple and Universal MCP Server to Debug Testbench Simulation Failures Via Log Parsing And Wave…☆62Jul 30, 2026Updated 3 weeks ago
- ☆61May 22, 2026Updated 3 months ago
- xverif is a local toolkit for chip-verification debug agents. It contains deterministic tools for design and waveform debug, coverage, bi…☆86Updated this week
- Extending BookSim2.0 and HotSpot6.0 for Power, Performance and Thermal evaluation of 3D NoC Architectures☆14Aug 9, 2019Updated 7 years ago
- ☆23Mar 19, 2026Updated 5 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Binary Single Precision Floating-point Fused Multiply-Add Unit Design (Verilog HDL)☆22Jul 8, 2013Updated 13 years ago
- A python project to automatically generate the UVM testbench document.☆21Feb 27, 2024Updated 2 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆11Oct 3, 2017Updated 8 years ago
- some gnu radio demo for antsdr☆18Nov 25, 2021Updated 4 years ago
- YAMM package repository☆34Mar 20, 2023Updated 3 years ago
- Syntacore first stage bootloader☆11Jan 19, 2026Updated 7 months ago
- Course content for the University of Bristol Design Verification course.☆64Oct 1, 2025Updated 10 months ago
- OpenExSys_NoC a mesh-based network on chip IP.☆21Dec 1, 2023Updated 2 years ago
- AI-Powered Hardware Design & Verification Copilot - Plugin for your CLI☆22Jul 12, 2026Updated last month
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- UVM interactive debug library☆36Feb 28, 2026Updated 5 months ago
- 面向 AI 编程 Agent 的开源形式验证技能库，聚焦 FPV、SVA、证明优化、TCL 脚本与可扩展的形式验证工作流。Open-source formal verification skills for AI coding agents, focused on FPV,…☆29Jul 27, 2026Updated 3 weeks ago
- This repository defines a Claude Code skill for working with Verilog☆18Apr 21, 2026Updated 4 months ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆25Mar 25, 2025Updated last year
- This is a uvm example. The video is available at https://www.bilibili.com/video/BV1yq4y177f6/☆52Mar 2, 2022Updated 4 years ago
- UCAS SEP扩展脚本 - 课程评估辅助 etc.☆13Apr 3, 2025Updated last year
- EpicSim Project☆71Mar 1, 2021Updated 5 years ago
- ☆20Jan 13, 2026Updated 7 months ago
- Agent skills for veriloga☆29Jul 21, 2026Updated last month
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Systemverilog DPI-C call Python function☆28Mar 11, 2021Updated 5 years ago
- VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a sta…☆45Aug 3, 2026Updated 3 weeks ago
- YosysHQ SVA AXI Properties☆54Feb 7, 2023Updated 3 years ago
- PyBitmessage API frontend for Android using QT5 and python 3☆11Oct 3, 2018Updated 7 years ago
- PoV mod for HoneySelect 2.☆12May 10, 2021Updated 5 years ago
- ☆10Jan 9, 2017Updated 9 years ago
- ☆54Jan 9, 2026Updated 7 months ago
- ☆10Apr 8, 2021Updated 5 years ago
- turbo 8051☆30Aug 30, 2017Updated 8 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- generate UVM testbench using python☆28Mar 24, 2018Updated 8 years ago
- ☆17Jul 17, 2025Updated last year
- An FPGA-based RISC-V CPU☆16Dec 7, 2021Updated 4 years ago
- Integer Multiplier Generator for Verilog☆25Jul 4, 2025Updated last year
- n-wise coverage tool for combinatorial testing☆11Sep 7, 2019Updated 6 years ago
- r2live相关论文、代码中文注释以及代码改动☆11Sep 24, 2021Updated 4 years ago
- ☆17Jan 7, 2023Updated 3 years ago