fucxy / PDA_SP

Related projects ⓘ

Alternatives and complementary repositories for PDA_SP

• yutongshen / RISC-V-Simulator
  ☆26Updated last year
• twweeb / VLSI-Physical-Design-Automation
  Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
  ☆42Updated 3 years ago
• cuhk-eda / REST
  REST, a reinforcement learning framework for constructing rectilinear Steiner Minimum tree (RSMT)
  ☆50Updated 2 years ago
• luckyrantanplan / nthu-route
  VLSI EDA Global Router
  ☆68Updated 6 years ago
• Daikon-Sun / Physical-Design-for-Nanometer-ICs
  Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)
  ☆39Updated 5 years ago
• gundambox / DIY_OpenMIPS
  實作《自己動手寫CPU》書上的程式碼
  ☆57Updated 6 years ago
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆23Updated 4 years ago
• The-OpenROAD-Project-Attic / flute3
  Flute3 is an open-source rectilinear Steiner minimum tree heuristic from Iowa State, with UFRGS improvements
  ☆24Updated 3 years ago
• ksettaluri6 / AutoCkt
  Deep Reinforcement Learning of Analog Circuit Designs
  ☆97Updated last year
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆34Updated 4 years ago
• kuopinghsu / srv32
  Simple 3-stage pipeline RISC-V processor
  ☆133Updated 5 months ago
• accomdemy / accomdemy_rv32i
  伴伴學 RISC-V RV32I Architecture CPU
  ☆24Updated 2 years ago
• mediaic / Crash_Course_for_New_Members
  Deep Learning & VLSI Crash Course for New Members
  ☆35Updated 3 months ago
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 4 years ago
• yutongshen / RISC-V_SoC
  ☆29Updated last year
• jacky860226 / nthu-route
  nthu-route 2.11
  ☆12Updated 5 years ago
• scale-lab / DRiLLS
  DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)
  ☆102Updated last year
• EricLu1218 / Physical_Design_Automation
  2019 NTHU CS6135 (CS613500) VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing …
  ☆29Updated 11 months ago
• levibyte / channel_router
  demo on simple channel router
  ☆12Updated 5 years ago
• DfX-NYUAD / Corblivar
  Corblivar is a simulated-annealing-based floorplanning suite for 3D ICs
  ☆26Updated 5 months ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆21Updated this week
• shahsaumya00 / D-Algorithm-Combinational
  Combinational ATPG generator based on D-Algorithm
  ☆15Updated 3 years ago
• gupta409 / Floorplanner
  Implementation of a Simulated Annealing based Floorplanner Tool for Chip Design Automation
  ☆8Updated 5 years ago
• NTU-LaDS-II / qATG
  An open-source quantum automatic test generator.
  ☆11Updated 2 months ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆52Updated 4 years ago
• Multimedia-Processing / Digital-Logic-Design
  透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。
  ☆15Updated last year
• UMN-EDA / BeGAN-benchmarks
  ☆25Updated last year
• shininglion / rectilinear_spanning_graph
  This library contains rectilinear spanning graph construction, finding minimum spanning tree and an implementation of binary search tree
  ☆9Updated 9 years ago
• ahmed-agiza / EDAViewer
  EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
  ☆68Updated last year
• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆27Updated 5 years ago