Basic Verilog modules
☆13Jul 8, 2021Updated 4 years ago
Alternatives and similar repositories for verilog-basics
Users that are interested in verilog-basics are comparing it to the libraries listed below
Sorting:
- ☆13Aug 17, 2021Updated 4 years ago
- A very simple SDRAM controller for FPGA written in Verilog. It exposes a SRAM-like interface to the rest of the FPGA fabric☆14Dec 4, 2018Updated 7 years ago
- A user-space port of the altera-stapl driver from the linux kernel☆14Jan 10, 2023Updated 3 years ago
- ☆11Nov 13, 2022Updated 3 years ago
- ☆10Nov 4, 2022Updated 3 years ago
- Golang package for PCI Express data transfers☆13Apr 24, 2018Updated 7 years ago
- ☆12Jul 17, 2016Updated 9 years ago
- Decrypts RSDF, CFF and DLC files using a web service☆15Nov 20, 2018Updated 7 years ago
- DMA core compatible with AHB3-Lite☆10Mar 30, 2019Updated 6 years ago
- A repository with some Deep Reinforcement Learning baselines written in julia using Flux.☆12Mar 28, 2023Updated 2 years ago
- ☆11Jun 7, 2018Updated 7 years ago
- ☆11Jul 4, 2023Updated 2 years ago
- Project Status: Discontinued, New repository: spec2rtl-plugin☆23Feb 1, 2026Updated last month
- ☆17Aug 7, 2023Updated 2 years ago
- Custom NERDTreeIgnore settings per project.☆11May 17, 2015Updated 10 years ago
- SystemVerilog package for reading, manipulating, and writing JSON-formatted data☆12Feb 19, 2022Updated 4 years ago
- Asynchronous FIFO for transferring data between two asynchronous clock domains☆17Jun 3, 2016Updated 9 years ago
- Export Telegram stickers to WhatsApp on iOS/Android☆20Feb 7, 2024Updated 2 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- General Public Not Unnecessary Death Declaration☆16Apr 26, 2016Updated 9 years ago
- Coverview☆28Jan 29, 2026Updated last month
- Designs for the Olimex iCE40HX1K-EVB board☆14Aug 14, 2017Updated 8 years ago
- OFS Platform Components☆19May 28, 2025Updated 9 months ago
- Fusesoc compatible rtl cores☆16Nov 23, 2022Updated 3 years ago
- Simulates a controller for games either over the network or locally.☆11Apr 2, 2018Updated 7 years ago
- Convert hexadecimal numbers to decimal and vice versa.☆14Aug 5, 2024Updated last year
- Quite OK image compression Verilog implementation☆23Nov 27, 2024Updated last year
- ☆29Jul 9, 2025Updated 7 months ago
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆76Feb 23, 2026Updated last week
- 2-channel microcontroller servo with EEM and Ethernet based on STM32 CPU☆22Jun 22, 2023Updated 2 years ago
- Decrypt DLC files with http://dcrypt.it/☆17Jan 4, 2023Updated 3 years ago
- An 8b10b decoder and encoder in logic in VHDL☆26Apr 12, 2021Updated 4 years ago
- HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.☆38Feb 28, 2026Updated last week
- 异步FIFO的内部实现☆25Aug 26, 2018Updated 7 years ago
- ☆18Jul 6, 2023Updated 2 years ago
- [Inactive] Simplified interface for a steam chat bot☆27Jun 3, 2017Updated 8 years ago
- GNOME Shell extension that adds a menu with all open windows☆20May 12, 2025Updated 9 months ago
- ☆14Jul 28, 2016Updated 9 years ago
- Synchronous FIFOs designed in Verilog/System Verilog.☆25Dec 21, 2025Updated 2 months ago