Alternatives and similar repositories for vscode-tcl:

Users that are interested in vscode-tcl are comparing it to the libraries listed below

• conej730 / vscode-tcl-debug
  Tcl Debug extension for VS Code
  ☆27Updated last year
• tcltk / tcllib
  tcllib (Mirror of core.tcl-lang.org).
  ☆144Updated last month
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆113Updated last week
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆56Updated 5 months ago
• verilog-to-routing / tatum
  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
  ☆56Updated 9 months ago
• bmpenuelas / systemverilog-formatter-vscode
  Beautify SystemVerilog code in VSCode through Verible
  ☆17Updated last month
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆22Updated 4 years ago
• ucb-art / BAG2_cds_ff_mpt
  BAG2 workspace for fake PDK (cds_ff_mpt)
  ☆55Updated 4 years ago
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆97Updated 4 months ago
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆100Updated last month
• bluecheetah / bag
  BAG framework
  ☆40Updated 7 months ago
• The-OpenROAD-Project / yosys
  Logic synthesis and ABC based optimization
  ☆49Updated last week
• efabless / mpw_precheck
  ☆37Updated 3 weeks ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆39Updated 11 months ago
• parallella / openeda
  Open source EDA chip design flow
  ☆50Updated 8 years ago
• gnucap / gnucap
  gnucap mirror (read only)
  ☆21Updated last week
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆58Updated last week
• ActiveState / tdk
  Tcl Dev Kit (TDK)
  ☆71Updated 10 months ago
• bmpenuelas / waveform-render-vscode
  Render waveforms inside VSCode with WaveDrom
  ☆36Updated 8 months ago
• ActiveState / teapot
  Tcl TEApot
  ☆46Updated 2 years ago
• google / skywater-pdk-libs-sky130_fd_sc_hd
  "High density" digital standard cells for SKY130 provided by SkyWater.
  ☆16Updated 2 years ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• byuccl / spydrnet
  A flexible framework for analyzing and transforming FPGA netlists. Official repository.
  ☆93Updated last month
• chipsalliance / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆35Updated this week
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 4 years ago
• chipsalliance / AIB-specification
  Home of the Advanced Interface Bus (AIB) specification.
  ☆50Updated 2 years ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆51Updated this week
• kevinpt / symbolator
  HDL symbol generator
  ☆189Updated 2 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• tcltk / tklib
  tklib (Mirror of core.tcl-lang.org)
  ☆49Updated this week