Alternatives and similar repositories for vscode-tcl

Users that are interested in vscode-tcl are comparing it to the libraries listed below

• conej730 / vscode-tcl-debug
  Tcl Debug extension for VS Code
  ☆27Updated 2 years ago
• tcltk / tcllib
  tcllib (Mirror of core.tcl-lang.org).
  ☆153Updated 2 months ago
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆127Updated 2 weeks ago
• RTimothyEdwards / XCircuit
  XCircuit circuit drawing and schematic capture tool
  ☆131Updated last month
• bmpenuelas / waveform-render-vscode
  Render waveforms inside VSCode with WaveDrom
  ☆38Updated last month
• gvekony / sv-1800-2012
  IEEE Std 1800™-2012: IEEE Standard for SystemVerilog -- Unified Hardware Design, Specification, and Verification Language syntax definiti…
  ☆32Updated last year
• wohali / vcd_parsealyze
  A Value Change Dump (VCD) file parser and analyzer
  ☆24Updated 5 years ago
• nmoroze / tclint
  Modern dev tools for Tcl • includes a linter, formatter, and editor integration.
  ☆81Updated this week
• thomasrussellmurphy / istyle-verilog-formatter
  Open source implementation of a Verilog formatter
  ☆183Updated 3 years ago
• ericsonj / vscode-verilogformar
  ☆11Updated last month
• ActiveState / tdk
  Tcl Dev Kit (TDK)
  ☆81Updated last year
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆104Updated last year
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated last month
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆23Updated 5 years ago
• edaplayground / eda-playground
  EDA Playground -- The FREE IDE for SystemVerilog, Verilog, and VHDL
  ☆66Updated 3 months ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆66Updated 6 years ago
• kevinpt / symbolator
  HDL symbol generator
  ☆200Updated 2 years ago
• TheOneKevin / icarusext
  iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.
  ☆11Updated 2 years ago
• KenKundert / svg_schematic
  Generate SVG schematics and block diagrams without a mouse.
  ☆31Updated 5 months ago
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆114Updated last year
• flightaware / tcl.gd
  Feature-complete Tcl interface to GD graphics drawing library
  ☆18Updated 4 years ago
• alemuller / tree-sitter-vhdl
  VHDL grammar for tree-sitter
  ☆32Updated 2 years ago
• TheClams / SystemVerilog
  SystemVerilog plugin for Sublime Text
  ☆49Updated 3 months ago
• bogdanvuk / pygears
  HW Design: A Functional Approach
  ☆146Updated 2 years ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆64Updated 2 years ago
• SanDisk-Open-Source / pyvcd
  Python package for writing Value Change Dump (VCD) files.
  ☆128Updated last year
• imr / ngspice
  mirror of ngspice repo at git://git.code.sf.net/p/ngspice/ngspice ngspice-ngspice
  ☆225Updated this week
• PacoReinaCampo / verilog2vhdl
  Hardware Description Language Translator
  ☆18Updated last week
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆72Updated this week
• slaclab / rogue
  SLAC Python Based Hardware Abstraction & Data Acquisition System
  ☆48Updated 2 weeks ago