Alternatives and similar repositories for vscode-tcl

Users that are interested in vscode-tcl are comparing it to the libraries listed below

• conej730 / vscode-tcl-debug
  Tcl Debug extension for VS Code
  ☆28Updated 2 years ago
• tcltk / tcllib
  tcllib (Mirror of core.tcl-lang.org).
  ☆148Updated 3 weeks ago
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆122Updated this week
• flightaware / tcl.gd
  Feature-complete Tcl interface to GD graphics drawing library
  ☆18Updated 3 years ago
• RTimothyEdwards / XCircuit
  XCircuit circuit drawing and schematic capture tool
  ☆123Updated 5 months ago
• TheOneKevin / icarusext
  iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.
  ☆11Updated 2 years ago
• ActiveState / tdk
  Tcl Dev Kit (TDK)
  ☆78Updated last year
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆56Updated 5 months ago
• puremourning / TclProDebug
  Upgrade of debugger from classic TclPro to Tcl 8.5+
  ☆19Updated 3 years ago
• bmpenuelas / waveform-render-vscode
  Render waveforms inside VSCode with WaveDrom
  ☆38Updated 4 months ago
• edaplayground / eda-playground
  EDA Playground -- The FREE IDE for SystemVerilog, Verilog, and VHDL
  ☆65Updated 2 months ago
• clin99 / awesome-eda
  ☆93Updated 6 years ago
• laurentc2 / FreePDK45_for_KLayout
  KLayout technology files for FreePDK45
  ☆22Updated 4 years ago
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆22Updated 5 years ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆66Updated this week
• ucb-art / BAG2_cds_ff_mpt
  BAG2 workspace for fake PDK (cds_ff_mpt)
  ☆59Updated 5 years ago
• nmoroze / tclint
  Modern dev tools for Tcl • includes a linter, formatter, and editor integration.
  ☆68Updated last month
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• ActiveState / teapot
  Tcl TEApot
  ☆50Updated 3 years ago
• gvekony / sv-1800-2012
  IEEE Std 1800™-2012: IEEE Standard for SystemVerilog -- Unified Hardware Design, Specification, and Verification Language syntax definiti…
  ☆32Updated 10 months ago
• steveicarus / ivtest
  Regression test suite for Icarus Verilog. (OBSOLETE)
  ☆115Updated 2 years ago
• flightaware / TclProDebug
  Upgrade of debugger from classic TclPro to Tcl 8.5+
  ☆37Updated 7 years ago
• The-OpenROAD-Project / OpenDB
  Database and Tool Framework for EDA
  ☆117Updated 4 years ago
• efabless / mpw_precheck
  ☆43Updated 6 months ago
• wrcad / xictools
  XicTools: Xic graphical editor, WRspice circuit simulator, and accessories. for electronic design.
  ☆174Updated this week
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆65Updated 5 years ago
• rubund / graywolf
  ☆112Updated 4 years ago
• KenKundert / svg_schematic
  Generate SVG schematics and block diagrams without a mouse.
  ☆29Updated 2 months ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated last year
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆108Updated 10 months ago