bitwisecook / vscode-tclLinks
Tcl for Visual Studio Code
☆42Updated last year
Alternatives and similar repositories for vscode-tcl
Users that are interested in vscode-tcl are comparing it to the libraries listed below
Sorting:
- Tcl Debug extension for VS Code☆27Updated 2 years ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆120Updated last month
- tcllib (Mirror of core.tcl-lang.org).☆145Updated last month
- Tcl Dev Kit (TDK)☆75Updated last year
- XCircuit circuit drawing and schematic capture tool☆119Updated 3 months ago
- Qrouter detail router for digital ASIC designs☆57Updated 3 months ago
- Logic synthesis and ABC based optimization☆49Updated this week
- SystemVerilog grammar for tree-sitter☆102Updated 8 months ago
- Home of the Advanced Interface Bus (AIB) specification.☆53Updated 2 years ago
- Index of the fully open source process design kits (PDKs) maintained by Google.☆99Updated 2 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Updated 2 years ago
- EDA Playground -- The FREE IDE for SystemVerilog, Verilog, and VHDL☆62Updated 2 weeks ago
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆64Updated last week
- Open source EDA chip design flow☆51Updated 8 years ago
- Beautify SystemVerilog code in VSCode through Verible☆20Updated 2 weeks ago
- IO and Pin Placer for Floorplan-Placement Subflow☆22Updated 4 years ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆64Updated 5 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆52Updated last year
- SystemRDL 2.0 language compiler front-end☆255Updated last week
- SystemVerilog support in VS Code☆141Updated 4 months ago
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆90Updated 10 months ago
- ☆113Updated 4 years ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆62Updated last year
- HDL symbol generator☆190Updated 2 years ago
- ADMS is a code generator for some of Verilog-A☆100Updated 2 years ago
- FPGA tool performance profiling☆102Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- ☆149Updated 2 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆221Updated 2 weeks ago
- GNU readline for interactive Tcl shells☆65Updated 4 months ago