nmoroze / tclintLinks
Modern dev tools for Tcl • includes a linter, formatter, and editor integration.
☆62Updated last week
Alternatives and similar repositories for tclint
Users that are interested in tclint are comparing it to the libraries listed below
Sorting:
- SystemVerilog grammar for tree-sitter☆105Updated 8 months ago
- Python bindings for slang, a library for compiling SystemVerilog☆62Updated 6 months ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆121Updated 2 months ago
- WAL enables programmable waveform analysis.☆155Updated 2 months ago
- Tools for working with circuits as graphs in python☆122Updated last year
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆224Updated last week
- Structural Netlist API (and more) for EDA post synthesis flow development☆112Updated this week
- magma circuits☆261Updated 9 months ago
- ☆112Updated 4 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆403Updated this week
- SystemVerilog frontend for Yosys☆148Updated last week
- Qrouter detail router for digital ASIC designs☆56Updated 3 months ago
- ☆78Updated last week
- ideas and eda software for vlsi design☆50Updated last week
- Hardware Description Library☆81Updated 3 months ago
- Announcements related to Verilator☆39Updated 5 years ago
- A command-line tool for displaying vcd waveforms.☆59Updated last year
- A Python to VHDL compiler☆16Updated 3 months ago
- ACT hardware description language and core tools.☆117Updated last week
- Simple parser for extracting VHDL documentation☆71Updated last year
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆227Updated this week
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆221Updated last week
- A Standalone Structural Verilog Parser☆96Updated 3 years ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆216Updated 9 months ago
- A SystemVerilog source file pickler.☆59Updated 9 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆154Updated last month
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆106Updated 4 years ago
- A standalone structural (gate-level) verilog parser☆38Updated 2 weeks ago
- Logic synthesis and ABC based optimization☆49Updated 3 weeks ago
- SystemVerilog synthesis tool☆206Updated 4 months ago