nmoroze / tclintLinks
Modern dev tools for Tcl • includes a linter, formatter, and editor integration.
☆55Updated 2 weeks ago
Alternatives and similar repositories for tclint
Users that are interested in tclint are comparing it to the libraries listed below
Sorting:
- SystemVerilog grammar for tree-sitter☆99Updated 6 months ago
- FPGA Assembly (FASM) Parser and Generator☆91Updated 2 years ago
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆117Updated 2 weeks ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Announcements related to Verilator☆39Updated 5 years ago
- ☆26Updated last month
- Python bindings for slang, a library for compiling SystemVerilog☆58Updated 4 months ago
- A standalone structural (gate-level) verilog parser☆35Updated 3 weeks ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆114Updated last year
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆223Updated last week
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆64Updated 2 weeks ago
- ☆79Updated last year
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆101Updated 4 months ago
- Tools for working with circuits as graphs in python☆120Updated last year
- A SystemVerilog source file pickler.☆57Updated 7 months ago
- ideas and eda software for vlsi design☆50Updated last week
- ☆40Updated 3 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆17Updated last month
- SystemVerilog frontend for Yosys☆117Updated last week
- A Standalone Structural Verilog Parser☆92Updated 3 years ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Running Python code in SystemVerilog☆69Updated this week
- Structural Netlist API (and more) for EDA post synthesis flow development☆103Updated last week
- Standard Cell Library based Memory Compiler using FF/Latch cells☆147Updated 11 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆60Updated 3 years ago
- SystemVerilog Linter based on pyslang☆30Updated last month
- ☆32Updated 4 months ago
- ☆56Updated 2 years ago
- WAL enables programmable waveform analysis.☆151Updated 3 months ago
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆61Updated last week