nmoroze / tclint
EDA-centric utility for linting and analyzing Tcl code.
☆34Updated last week
Alternatives and similar repositories for tclint:
Users that are interested in tclint are comparing it to the libraries listed below
- fakeram generator for use by researchers who do not have access to commercial ram generators☆34Updated 2 years ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆43Updated 4 years ago
- Introductory course into static timing analysis (STA).☆79Updated 2 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆75Updated 10 months ago
- Mirror of Synopsys's Liberty parser library☆19Updated 6 years ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆34Updated last week
- Python bindings for slang, a library for compiling SystemVerilog☆55Updated last week
- ☆31Updated 3 weeks ago
- ideas and eda software for vlsi design☆48Updated 3 weeks ago
- Python library for operations with VCD and other digital wave files☆47Updated 7 months ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆107Updated last year
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆24Updated 3 years ago
- ☆121Updated 6 months ago
- ☆55Updated this week
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆60Updated 3 months ago
- ☆45Updated 8 years ago
- ☆40Updated 6 years ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆57Updated 7 months ago
- SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)☆74Updated 4 years ago
- SKY130 SRAM macros generated by SRAM 22☆11Updated last week
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆55Updated last month
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆42Updated 2 weeks ago
- reference block design for the ASAP7nm library in Cadence Innovus☆33Updated 7 months ago
- Python wrapper for verilator model☆79Updated 11 months ago
- Cocotb AHB Extension - AHB VIP☆13Updated this week
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆51Updated 4 months ago
- IDEA project source files☆102Updated 2 months ago
- ☆39Updated 4 months ago
- Mirror of the Universal Verification Methodology from sourceforge☆33Updated 10 years ago
- Python Tool for UVM Testbench Generation☆50Updated 8 months ago