Alternatives and similar repositories for tclint

Users that are interested in tclint are comparing it to the libraries listed below

• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆109Updated 11 months ago
• najaeda / naja
  Structural Netlist API (and more) for EDA post synthesis flow development
  ☆119Updated last month
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆64Updated 9 months ago
• phanrahan / magma
  magma circuits
  ☆262Updated last year
• circuitgraph / circuitgraph
  Tools for working with circuits as graphs in python
  ☆125Updated last year
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆157Updated last week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆235Updated last month
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆166Updated this week
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆123Updated this week
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆63Updated last year
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆226Updated last week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• jonpry / Pill
  Skill language interpreter
  ☆70Updated 5 years ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆97Updated 3 years ago
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆84Updated 6 months ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆41Updated 5 years ago
• parallaxsw / OpenSTA
  ☆90Updated this week
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated last week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆215Updated 7 months ago
• pieter3d / simview
  ☆85Updated last week
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆164Updated last month
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆422Updated last month
• raczben / fliplot
  HTML & Js based VCD viewer
  ☆65Updated 2 months ago
• zeroasiccorp / ebrick-demo
  Demo: how to create a custom EBRICK
  ☆23Updated 11 months ago
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆79Updated 3 years ago
• rubund / graywolf
  ☆112Updated 4 years ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆68Updated 3 weeks ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆150Updated 2 weeks ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆218Updated this week
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆158Updated 3 weeks ago