edaplayground / eda-playgroundView external linksLinks
EDA Playground -- The FREE IDE for SystemVerilog, Verilog, and VHDL
☆67Feb 4, 2026Updated last week
Alternatives and similar repositories for eda-playground
Users that are interested in eda-playground are comparing it to the libraries listed below
Sorting:
- EPWave -- The Free Interactive Browser-Based Wave Viewer☆14Apr 1, 2015Updated 10 years ago
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Feb 13, 2020Updated 6 years ago
- An online Verilog IDE based on YosysJS.☆24Jan 7, 2016Updated 10 years ago
- Open Source PHY v2☆33Apr 25, 2024Updated last year
- SystemVerilog wrapper over the Verilog Programming Interface (VPI)☆13Jun 3, 2025Updated 8 months ago
- Latest in the line of the E32 processors with better/generic cache placement☆10Feb 25, 2023Updated 2 years ago
- 🕒 Static Timing Analysis diagram renderer☆13Dec 13, 2023Updated 2 years ago
- Reflection API for SystemVerilog☆15Jun 5, 2025Updated 8 months ago
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15May 21, 2018Updated 7 years ago
- IP-XACT XML binding library☆16Jun 23, 2016Updated 9 years ago
- Advanced Debug Interface☆14Jan 23, 2025Updated last year
- ☆33Oct 4, 2017Updated 8 years ago
- Semi-private RTL development upstream of OpenCPI - this is *not* the OpenCPI repo!☆25Oct 19, 2016Updated 9 years ago
- ☆114Nov 11, 2025Updated 3 months ago
- Magic VLSI Layout Tool☆21Oct 10, 2019Updated 6 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆60Feb 25, 2023Updated 2 years ago
- A header only C++11 library for functional coverage☆36Oct 5, 2022Updated 3 years ago
- Revision Control Labs and Materials☆25Jan 23, 2018Updated 8 years ago
- Axiom Alpha prototype hardware source files (electronic schematics, documentation, PCB layouts, etc.)☆22Jun 10, 2014Updated 11 years ago
- Libre Silicon Compiler☆22Apr 13, 2021Updated 4 years ago
- A generic class library in SystemVerilog☆87May 20, 2021Updated 4 years ago
- Axiom Alpha prototype software (FPGA, Linux, etc.)☆30Dec 9, 2015Updated 10 years ago
- Theia: ray graphic processing unit☆20Jul 17, 2014Updated 11 years ago
- UVM 1.2 port to Python☆259Feb 9, 2025Updated last year
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Nov 12, 2025Updated 3 months ago
- ☆60May 11, 2016Updated 9 years ago
- 根据最近看的一本书编写的对应RTL以及Testbench☆20Mar 12, 2017Updated 8 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆138Feb 3, 2026Updated last week
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- Arizona State University CSE320☆11Mar 22, 2015Updated 10 years ago
- Tools for SystemVerilog development.☆15Jan 3, 2018Updated 8 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- APB Timer Unit☆13Oct 30, 2025Updated 3 months ago
- WebCL conformance tests☆20Feb 9, 2018Updated 8 years ago
- Python Verilog-AMS Parser☆12Oct 13, 2015Updated 10 years ago
- ☆12Feb 6, 2026Updated last week
- This is the repository for the IEEE version of the book☆80Sep 29, 2020Updated 5 years ago
- Test suite designed to check compliance with the SystemVerilog standard.☆356Updated this week
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 3 years ago