edaplayground / eda-playground
EDA Playground -- The FREE IDE for SystemVerilog, Verilog, and VHDL
☆53Updated 3 weeks ago
Related projects ⓘ
Alternatives and complementary repositories for eda-playground
- Python packages providing a library for Verification Stimulus and Coverage☆113Updated last month
- ☆73Updated last year
- A complete open-source design-for-testing (DFT) Solution☆135Updated last week
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆195Updated 3 weeks ago
- SystemRDL 2.0 language compiler front-end☆233Updated 2 months ago
- Ariane is a 6-stage RISC-V CPU☆122Updated 4 years ago
- FPGA tool performance profiling☆101Updated 8 months ago
- Fabric generator and CAD tools☆148Updated this week
- Test suite designed to check compliance with the SystemVerilog standard.☆295Updated this week
- ☆184Updated this week
- Control and status register code generator toolchain☆101Updated 2 months ago
- ☆55Updated 2 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆201Updated last month
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆129Updated last week
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆56Updated 3 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆150Updated last year
- ☆120Updated 2 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆133Updated 4 months ago
- UVM 1.2 port to Python☆242Updated 7 months ago
- A Fast, Low-Overhead On-chip Network☆136Updated 3 weeks ago
- Network on Chip Implementation written in SytemVerilog☆157Updated 2 years ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆104Updated 11 months ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆127Updated last month
- ☆42Updated 8 years ago
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 3 years ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆363Updated this week
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆98Updated 3 years ago
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆202Updated 2 weeks ago
- Introductory course into static timing analysis (STA).☆64Updated last week
- Announcements related to Verilator☆38Updated 4 years ago