Alternatives and similar repositories for eda-playground

Users that are interested in eda-playground are comparing it to the libraries listed below

• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆60Updated 4 years ago
• chipsalliance / uvm-verilator
  ☆96Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆136Updated last week
• accellera-official / uvm-core
  ☆86Updated 9 months ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆102Updated last month
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆199Updated 8 months ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆178Updated this week
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆123Updated 3 weeks ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆94Updated 3 weeks ago
• raysalemi / Python4RTLVerification
  ☆160Updated 2 years ago
• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆254Updated 3 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆138Updated last month
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆132Updated 6 years ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆48Updated 5 months ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆83Updated 4 years ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 5 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆144Updated last month
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆79Updated 8 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆105Updated 3 years ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆160Updated 3 weeks ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 5 years ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated last week
• accellera / uvm
  ☆54Updated 9 years ago
• chipsalliance / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆39Updated 3 weeks ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆81Updated 2 months ago
• svunit / svunit
  ☆201Updated 3 months ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆115Updated this week
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆187Updated 2 weeks ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆252Updated 4 months ago