Alternatives and similar repositories for eda-playground

Users that are interested in eda-playground are comparing it to the libraries listed below

• SystemRDL / systemrdl-compiler
  SystemRDL 2.0 language compiler front-end
  ☆257Updated last month
• Juniper / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆201Updated 10 months ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆216Updated last month
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆126Updated last month
• chipsalliance / uvm-verilator
  ☆97Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆139Updated last month
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆102Updated 3 months ago
• raysalemi / Python4RTLVerification
  ☆164Updated 2 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated 2 weeks ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆135Updated last year
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆164Updated last week
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆140Updated 11 months ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆253Updated 6 months ago
• svunit / svunit
  ☆206Updated 6 months ago
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆224Updated 2 weeks ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆116Updated last year
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆190Updated 3 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆174Updated 9 months ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆65Updated last month
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆229Updated last week
• kunalg123 / vsdflow
  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…
  ☆163Updated 2 years ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆143Updated last week
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆112Updated last week
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆83Updated 4 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆147Updated 3 months ago
• accellera-official / uvm-core
  ☆94Updated last year
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆143Updated 5 years ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆107Updated 2 years ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆290Updated 3 months ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆97Updated last month