edaplayground / eda-playgroundLinks
EDA Playground -- The FREE IDE for SystemVerilog, Verilog, and VHDL
☆66Updated 3 months ago
Alternatives and similar repositories for eda-playground
Users that are interested in eda-playground are comparing it to the libraries listed below
Sorting:
- SystemRDL 2.0 language compiler front-end☆269Updated last month
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆207Updated last year
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆221Updated 3 weeks ago
- Python packages providing a library for Verification Stimulus and Coverage☆135Updated last month
- A complete open-source design-for-testing (DFT) Solution☆176Updated 4 months ago
- ☆113Updated 2 months ago
- Announcements related to Verilator☆43Updated 2 months ago
- RISC-V Verification Interface☆136Updated last month
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated 2 months ago
- Code used in☆200Updated 8 years ago
- Python-based IP-XACT parser and utilities☆142Updated last year
- ideas and eda software for vlsi design☆51Updated this week
- An Open-Source Design and Verification Environment for RISC-V☆86Updated 4 years ago
- FuseSoC standard core library☆151Updated last month
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆79Updated last year
- ☆174Updated 3 years ago
- ☆99Updated 4 months ago
- Basic RISC-V Test SoC☆166Updated 6 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆194Updated last month
- ☆208Updated 10 months ago
- Generate UVM register model from compiled SystemRDL input☆60Updated last month
- ☆60Updated 9 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆145Updated last year
- ☆106Updated last year
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆145Updated last week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆243Updated 4 months ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆163Updated 2 years ago
- Examples and reference for System Verilog Assertions☆89Updated 8 years ago
- UVM 1.2 port to Python☆257Updated 11 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆282Updated 5 years ago