Alternatives and similar repositories for vscode-tcl-debug

Users that are interested in vscode-tcl-debug are comparing it to the libraries listed below

• bitwisecook / vscode-tcl
  Tcl for Visual Studio Code
  ☆43Updated 2 years ago
• tcltk / tcllib
  tcllib (Mirror of core.tcl-lang.org).
  ☆148Updated last month
• coverify / euvm
  Embedded UVM (D Language port of IEEE UVM 1.0)
  ☆32Updated 4 months ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆76Updated 5 months ago
• ActiveState / tdk
  Tcl Dev Kit (TDK)
  ☆80Updated last year
• legoritma / ipxact-register-generator
  IPXACT Register Map Generator
  ☆11Updated 4 years ago
• edaplayground / eda-playground
  EDA Playground -- The FREE IDE for SystemVerilog, Verilog, and VHDL
  ☆66Updated 2 weeks ago
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆231Updated this week
• rochus-keller / Verilog
  This is the Verilog 2005 parser used by VerilogCreator
  ☆15Updated 6 years ago
• Minres / SystemC-Quickstart
  A simple C++ CMake project to jump-start development of SystemC models and systems
  ☆28Updated 10 months ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆40Updated 5 years ago
• SpinalHDL / CocotbLib
  ☆18Updated 2 months ago
• wohali / vcd_parsealyze
  A Value Change Dump (VCD) file parser and analyzer
  ☆23Updated 5 years ago
• rubund / graywolf
  ☆112Updated 4 years ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆67Updated this week
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆19Updated 11 months ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆97Updated 3 years ago
• flightaware / tclreadline
  GNU readline for interactive Tcl shells
  ☆68Updated last month
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆90Updated 4 years ago
• freecores / sparc64soc
  OpenSPARC-based SoC
  ☆70Updated 11 years ago
• steveicarus / ivtest
  Regression test suite for Icarus Verilog. (OBSOLETE)
  ☆115Updated 2 years ago
• tilk / yosys2digitaljs
  Export netlists from Yosys to DigitalJS
  ☆51Updated last month
• The-OpenROAD-Project / yosys
  Logic synthesis and ABC based optimization
  ☆49Updated last month
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• vsdip / rvmyth_avsddac_interface
  ☆15Updated 3 years ago
• RTimothyEdwards / XCircuit
  XCircuit circuit drawing and schematic capture tool
  ☆125Updated 5 months ago
• cambridgehackers / open-src-cvc
  Mirror of tachyon-da cvc Verilog simulator
  ☆47Updated 2 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆28Updated 3 years ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆65Updated 7 years ago
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆69Updated 9 months ago