Alternatives and similar repositories for vscode-tcl-debug

Users that are interested in vscode-tcl-debug are comparing it to the libraries listed below

• bitwisecook / vscode-tcl
  Tcl for Visual Studio Code
  ☆43Updated 2 years ago
• tcltk / tcllib
  tcllib (Mirror of core.tcl-lang.org).
  ☆153Updated last month
• coverify / euvm
  Embedded UVM (D Language port of IEEE UVM 1.0)
  ☆33Updated 3 weeks ago
• rochus-keller / Verilog
  This is the Verilog 2005 parser used by VerilogCreator
  ☆15Updated 6 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆75Updated 7 months ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆98Updated 3 years ago
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆238Updated last week
• libresilicon / qtflow
  Free open source EDA tools
  ☆66Updated 6 years ago
• rubund / graywolf
  ☆113Updated 4 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆89Updated 5 years ago
• ActiveState / tdk
  Tcl Dev Kit (TDK)
  ☆81Updated last year
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated 3 weeks ago
• PacoReinaCampo / verilog2vhdl
  Hardware Description Language Translator
  ☆18Updated 6 months ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆72Updated last week
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆35Updated 3 weeks ago
• torc-isi / torc
  Torc: Tools for Open Reconfigurable Computing
  ☆39Updated 8 years ago
• Minres / SystemC-Quickstart
  A simple C++ CMake project to jump-start development of SystemC models and systems
  ☆29Updated last year
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆23Updated 5 years ago
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆126Updated last week
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆79Updated 3 years ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆66Updated 7 years ago
• edaplayground / eda-playground
  EDA Playground -- The FREE IDE for SystemVerilog, Verilog, and VHDL
  ☆66Updated 2 months ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆43Updated last month
• chipsalliance / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆41Updated this week
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆63Updated 2 years ago
• freecores / i2c_master_slave_core
  I2C master/slave Core
  ☆13Updated 11 years ago
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆19Updated last year
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆17Updated 3 weeks ago
• antmicro / renode-verilator-integration
  This repository contains sample code integrating Renode with Verilator
  ☆25Updated 6 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆238Updated 2 months ago