Alternatives and similar repositories for vscode-tcl-debug

Users that are interested in vscode-tcl-debug are comparing it to the libraries listed below

• bitwisecook / vscode-tcl
  Tcl for Visual Studio Code
  ☆43Updated 2 years ago
• rochus-keller / Verilog
  This is the Verilog 2005 parser used by VerilogCreator
  ☆15Updated 6 years ago
• coverify / euvm
  Embedded UVM (D Language port of IEEE UVM 1.0)
  ☆32Updated 4 months ago
• tcltk / tcllib
  tcllib (Mirror of core.tcl-lang.org).
  ☆149Updated 2 months ago
• Minres / SystemC-Quickstart
  A simple C++ CMake project to jump-start development of SystemC models and systems
  ☆28Updated 11 months ago
• riscv-software-src / riscv-config
  RISC-V Configuration Validator
  ☆79Updated 6 months ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆75Updated 5 months ago
• edaplayground / eda-playground
  EDA Playground -- The FREE IDE for SystemVerilog, Verilog, and VHDL
  ☆66Updated last month
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆65Updated 5 years ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆97Updated 3 years ago
• TheOneKevin / icarusext
  iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.
  ☆11Updated 2 years ago
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆19Updated 11 months ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated last month
• ActiveState / tdk
  Tcl Dev Kit (TDK)
  ☆80Updated last year
• cambridgehackers / open-src-cvc
  Mirror of tachyon-da cvc Verilog simulator
  ☆48Updated 2 years ago
• kactus2 / kactus2dev
  Kactus2 is a graphical EDA tool based on the IP-XACT standard.
  ☆235Updated this week
• riscv / riscv-test-env
  ☆50Updated last month
• chipsalliance / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆41Updated this week
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆89Updated 5 years ago
• Nic30 / hwt
  VHDL/Verilog/SystemC code generator, simulator API written in python/c++
  ☆218Updated this week
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆86Updated 4 years ago
• embecosm / esp1-systemc-tlm
  Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 models
  ☆17Updated 12 years ago
• rubund / graywolf
  ☆112Updated 4 years ago
• legoritma / ipxact-register-generator
  IPXACT Register Map Generator
  ☆11Updated 4 years ago
• Huawei / fpga-accel
  The official repository of the local FPGA Development Kit.
  ☆19Updated 6 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆28Updated 3 years ago
• openpower-cores / a2o
  ☆140Updated 3 years ago
• socrocket / core
  SoCRocket - Core Repository
  ☆38Updated 8 years ago
• tianrenz2 / Single-Cycle-Processor
  Single-Cycle RISC-V Processor in systemverylog
  ☆24Updated 6 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆88Updated last year