Alternatives and similar repositories for vj-uart:

Users that are interested in vj-uart are comparing it to the libraries listed below

• thotypous / alterajtaguart
  Altera JTAG UART wrapper for Bluespec
  ☆24Updated 10 years ago
• GeezerGeek / open_sld
  Direct Python interface to Altera SLD Mega-function
  ☆20Updated 10 years ago
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆33Updated 6 years ago
• knielsen / ice40_viewer
  ☆58Updated last year
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆74Updated last year
• lawrie / tiny_usb_examples
  Using the TinyFPGA BX USB code in user designs
  ☆49Updated 5 years ago
• gtjennings1 / UPDuino-LH154Q01-Display
  Design to connect Lattice Ultraplus FPGA to LH154Q01 Display
  ☆28Updated 6 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆83Updated 6 years ago
• RISCV-on-Microsemi-FPGA / SoftConsole
  Eclipse based IDE for RISC-V bare metal software development.
  ☆18Updated 5 years ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆37Updated 7 years ago
• skristiansson / wb_sdram_ctrl
  SDRAM controller with multiple wishbone slave ports
  ☆28Updated 6 years ago
• projf / fpgatools
  Tools for FPGA development.
  ☆44Updated last year
• hamsternz / FPGA_GigabitTx
  Sending UDP packets out over a Gigabit PHY with an FPGA.
  ☆42Updated 8 years ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆65Updated 3 years ago
• rajesh-s / axi_cheatsheet
  A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)
  ☆26Updated 6 years ago
• brouhaha / xchange
  Change part number or package in a Xilinx 7-series FPGA bitstream
  ☆36Updated 4 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆45Updated 2 months ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆113Updated last year
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated 2 weeks ago
• bonfireprocessor / bonfire-cpu
  FPGA optimized RISC-V (RV32IM) implemenation
  ☆33Updated 4 years ago
• no2fpga / no2usb
  Nitro USB FPGA core
  ☆84Updated 10 months ago
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆44Updated 4 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆38Updated 7 months ago
• rohitk-singh / usb-device
  USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface
  ☆12Updated 7 years ago
• cliffordwolf / icotools
  Tools and Examples for IcoBoard
  ☆79Updated 3 years ago
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆85Updated 4 months ago
• HarmonInstruments / verilog
  ☆20Updated 2 years ago