Alternatives and similar repositories for vj-uart:

Users that are interested in vj-uart are comparing it to the libraries listed below

• GeezerGeek / open_sld
  Direct Python interface to Altera SLD Mega-function
  ☆20Updated 10 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆21Updated 5 years ago
• thotypous / alterajtaguart
  Altera JTAG UART wrapper for Bluespec
  ☆24Updated 11 years ago
• knielsen / ice40_viewer
  ☆59Updated last year
• lawrie / tiny_usb_examples
  Using the TinyFPGA BX USB code in user designs
  ☆49Updated 6 years ago
• projf / fpgatools
  Tools for FPGA development.
  ☆44Updated last year
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆85Updated 6 years ago
• cliffordwolf / icotools
  Tools and Examples for IcoBoard
  ☆80Updated 3 years ago
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆40Updated 5 years ago
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆34Updated 6 years ago
• olofk / observer
  ☆41Updated 4 years ago
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆87Updated 6 months ago
• DaveBerkeley / serv_soc
  SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
  ☆30Updated 4 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆42Updated 11 months ago
• noasic / noasic
  An open-source VHDL library for FPGA design.
  ☆31Updated 2 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated 2 weeks ago
• folknology / IceCore
  IceCore Ice40 HX based modular core
  ☆46Updated 4 years ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆47Updated 4 months ago
• AnttiLukats / HackaZynq
  Open Source ZYNQ Board
  ☆31Updated 9 years ago
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆77Updated last year
• smunaut / iua
  ice40 USB Analyzer
  ☆58Updated 4 years ago
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆36Updated 4 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• gtjennings1 / UPDuino-LH154Q01-Display
  Design to connect Lattice Ultraplus FPGA to LH154Q01 Display
  ☆28Updated 6 years ago
• brouhaha / xchange
  Change part number or package in a Xilinx 7-series FPGA bitstream
  ☆37Updated 4 years ago
• Cognoscan / BoostDSP
  VHDL Library for implementing common DSP functionality.
  ☆27Updated 6 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆61Updated 6 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆113Updated last year
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆38Updated last year