☆64Sep 4, 2026Updated 2 months ago
Alternatives and similar repositories for eth_100g
Users that are interested in eth_100g are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- NEORV32 RISC-V SoC running Zephyr RTOS on FPGA bare metal - with an extensible accelerator pipeline architecture, including an DMA-enable…☆18Aug 16, 2026Updated 2 months ago
- A PCIe RTL implementation☆27Aug 16, 2026Updated 2 months ago
- Hardware Acceleration☆17Nov 1, 2026Updated last week
- Source-available SystemVerilog RTL for a custom FPGA Ethernet datapath with ARP, IPv4, UDP, and specialized TCP transport control.☆42Jul 30, 2026Updated 3 months ago
- See and review any Vivado / Zynq / PYNQ project: drill-down Vivado-style diagrams and clock-domain, constraint and overlay checks for AI …☆27Nov 1, 2026Updated last week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI☆138Updated this week
- Create a working Rocket Chip bitstream for Xilinx boards on Ubuntu 24.04 LTS by Eugene Tarassov's GitHub repo☆11Apr 27, 2025Updated last year
- ☆11Jul 9, 2025Updated last year
- Bilingual FPGA-based SDR course for Zynq with labs, hardware workflow, MATLAB/Simulink and DSP implementation track☆109Updated this week
- openENOC is an open-source Ethernet-based NoC for scalable MPSoC systems, using Layer-2 frame switching to connect CPUs, accelerators and…☆28Updated this week
- ☆11Nov 17, 2025Updated 11 months ago
- Free, open-source EDA platform for VHDL and Verilog. HDL editor, circuit canvas, RTL viewer, waveform viewer, and FPGA toolchain in one…☆180Aug 20, 2026Updated 2 months ago
- This repository contains examples showing how to use the Arm CMSIS Debugger with Zephyr-based projects.☆17Sep 30, 2026Updated last month
- ☆15Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Precision Rectifier for Current Transformer☆10May 11, 2020Updated 6 years ago
- Run full applications in RAM on an STM32 ARM MCU☆12Sep 28, 2026Updated last month
- Compiler for ManiT, a systems language whose native number system is balanced ternary (−1, 0, +1). Two backends: LLVM for native executio…☆22Sep 15, 2026Updated last month
- USB2 core for LiteX☆12Sep 30, 2026Updated last month
- 64-bit RISC-V (RV64GC) core that boots Linux on an Arty A7 FPGA. Designed entirely by Claude Code: the specifications, RTL, verification …☆168Oct 20, 2026Updated 2 weeks ago
- ☆72Jul 13, 2026Updated 3 months ago
- WaveEye is an AXI4-Lite protocol root cause analysis tool that explains why a violation must occur by identifying missing inter-FSM depen…☆13Mar 30, 2026Updated 7 months ago
- Additional resources for simulation and testing of OpenROM that are not included in the OpenRAM repo.☆12May 14, 2025Updated last year
- A terminal based digital waveform viewer for Hardcaml☆17Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- zynq based high speed design☆14Feb 11, 2026Updated 8 months ago
- Translator for SystemVerilog DUT code to gHDL compatible VHDL code.☆28Updated this week
- Utilities for Avalon Memory Map☆11Jun 16, 2026Updated 4 months ago
- A Verilog implementation of Multi-bit-throughput LFSR with an detailed document about LFSRs for HW design engineers☆10Jan 2, 2026Updated 10 months ago
- Simple UVM environment for experimenting with Verilator.☆54Sep 9, 2026Updated 2 months ago
- FPGA implementation of radar v3☆112Aug 11, 2026Updated 2 months ago
- Arduino and Raspberry PI Development Kit☆10Jun 28, 2017Updated 9 years ago
- SystemVerilog AXI verification library and video-DMA IP: AXI4/Lite/Stream BFMs, triple-buffer VDMA, and multi-tap temporal VDMA with byte…☆30Jul 5, 2026Updated 4 months ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆37Jul 17, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Yocto port of luckfox-pico SDK☆11Feb 12, 2026Updated 8 months ago
- 🚀 Real-Time High-Level Synthesis (HLS) Projects for UltraScale+ FPGAs. Accelerated design pipelines, dataflow architectures, and low-lat…☆16Aug 2, 2026Updated 3 months ago
- ☆22Oct 13, 2026Updated 3 weeks ago
- FPGA USB 1.1 Low-Speed Implementation☆36Oct 3, 2018Updated 8 years ago
- Open Logic FPGA Standard Library☆1,033Updated this week
- Tiny Tapeout Explorer is an interactive web-based visualization tool for exploring integrated circuit designs from the Tiny Tapeout commu…☆25Updated this week
- ☆19Nov 1, 2025Updated last year
Are these results useful?