ZiyangYE / LicheeTang20K_DDR_TestLinks
The DDR Test Firmware for LicheeTang20K.
☆17Updated 2 years ago
Alternatives and similar repositories for LicheeTang20K_DDR_Test
Users that are interested in LicheeTang20K_DDR_Test are comparing it to the libraries listed below
Sorting:
- WCH CH569 SerDes Reverse Engineering☆30Updated 3 years ago
- RiscV based SOC with 2D and 3D graphics acceleration for Tang Nano 20K☆41Updated last year
- tang-nano-4K mini samples☆13Updated 3 years ago
- ☆21Updated 4 years ago
- ☆105Updated 2 years ago
- Xilinx 14.7 patch for Win10 32/64☆31Updated 3 years ago
- Tiny tips for Colorlight i5 FPGA board☆62Updated 4 years ago
- USB3 super speed development board useful as FPGA expansion based on WCH-Tech CH569☆27Updated 3 years ago
- Lichee Tang FPGA board examples☆32Updated 7 years ago
- Test code to talk from STM32 MCU over FSMC to SDRAM on ICE40 FPGA☆29Updated 9 years ago
- An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA☆88Updated 3 years ago
- ESP8266 Xilinx Virtual Cable - wifi JTAG☆40Updated 4 years ago
- Update IceStudio to support ColorLight 5A-75X, i5 and ICeSugar Pro FPGA boards☆50Updated 2 years ago
- 100BASE-FX Transmitter on RP2040☆24Updated last year
- A flexible, simple, yet powerful FPGA development board.☆17Updated 7 years ago
- fpga i2c rtc oled based clock with alarm supports buzzer☆16Updated 4 years ago
- High Speed Data Acquisition over HDMI - FPGA implementation☆49Updated last month
- Tutorials centred around Gowin FPGA parts for the /r/GowinFPGA subreddit☆60Updated last year
- A complete HDMI transmitter implementation in VHDL☆21Updated 6 months ago
- Xilinx Virtual Cable implementation for ESP32☆37Updated 4 years ago
- AGM bitstream utilities and decoded files from Supra☆46Updated 4 months ago
- community projects that can be used with the ULX3S FPGA ESP32 board☆17Updated last year
- Board definition files and initial example programs☆16Updated 4 years ago
- ESP8266 powered Xilinx Virtual Cable - Xilinx WiFi JTAG!☆30Updated 4 years ago
- An attempt to reverse engineer a bitstream made for an AL3-10 FPGA☆16Updated 2 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆66Updated 2 years ago
- ULPI Link Wrapper (USB Phy Interface)☆34Updated 5 years ago
- ☆45Updated 2 years ago
- Use Raspberry Pi as a wireless Xilinx JTAG 'cable'. Note: This is a portable, tested, maintained clone of https://github.com/strongleg/xv…☆45Updated 4 years ago
- Example Verilog code for Ulx3s☆41Updated 3 years ago