Change part number or package in a Xilinx 7-series FPGA bitstream
☆47Apr 27, 2020Updated 6 years ago
Alternatives and similar repositories for xchange
Users that are interested in xchange are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Next-Generation FPGA Place-and-Route☆10Aug 1, 2018Updated 8 years ago
- PCIe stack written in Amaranth.☆18Apr 27, 2026Updated 6 months ago
- nextpnr portable FPGA place and route tool☆11Nov 30, 2020Updated 5 years ago
- rust ftdi ft60x libusb driver☆16Dec 16, 2020Updated 5 years ago
- Documenting the Anlogic FPGA bit-stream format.☆92Dec 25, 2022Updated 3 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- SDI interface board for the apertus° AXIOM beta camera☆13Jan 19, 2019Updated 7 years ago
- ☆64Jul 21, 2020Updated 6 years ago
- 360nosc0pe Siglent SDS 1x0xX-E FPGA bitstreams☆18Aug 13, 2018Updated 8 years ago
- lightweight open HLS for FPGA rapid prototyping☆20Mar 22, 2018Updated 8 years ago
- Small Stack-Based Computer Compiler -- Verilog micro controller for FPGA housekeeping with peripherals☆16Jan 11, 2020Updated 6 years ago
- Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…☆12Mar 6, 2019Updated 7 years ago
- PCIe to .1 inch header breakout☆11Sep 14, 2020Updated 6 years ago
- TinyTapeout2 Super Slow Serial SRAM FPGA☆12Dec 2, 2022Updated 3 years ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Jul 7, 2022Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Xilinx Virtual Cable Daemon☆20Nov 20, 2019Updated 6 years ago
- Design files for my 3rd ultrasonic phased array. Will add gerbers etc. as I can guarantee they are correct.☆12Jul 23, 2018Updated 8 years ago
- Register access layer in Rust for all STM32 microcontrollers☆34Jul 10, 2022Updated 4 years ago
- SystemVerilog language server, based on Slang. Focuses on stability, performance and accuracy.☆12Aug 30, 2026Updated 2 months ago
- Device Include files for Padauk MCUs☆13Jun 10, 2023Updated 3 years ago
- not infinite, but huge canvas collaborative vector drawing program☆13Oct 28, 2018Updated 8 years ago
- photonSDI - an open source SDI core☆11May 26, 2021Updated 5 years ago
- Test/demo waveform datasets for libscopehal and glscopeclient☆12Oct 5, 2023Updated 3 years ago
- Coherent M-ary FSK Modulator/Demodulator, entirely in Python.☆24Feb 15, 2014Updated 12 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Betrusted embedded controller (UP5K)☆50Dec 22, 2023Updated 2 years ago
- A ROM Emulator for the HP-71B☆13Feb 26, 2026Updated 8 months ago
- A Verilog implementation of DisplayPort protocol for FPGAs☆276Mar 15, 2019Updated 7 years ago
- ☆18May 24, 2021Updated 5 years ago
- AXI Formal Verification IP☆25Apr 28, 2021Updated 5 years ago
- Reverse-engineering a vector format☆12Nov 28, 2020Updated 5 years ago
- ☆26Sep 27, 2018Updated 8 years ago
- My pergola FPGA projects☆30Jun 23, 2021Updated 5 years ago
- enclosure for the mainboard and zturn lite☆13Mar 13, 2020Updated 6 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Open source implementation of a x86 processor http://zet.aluzina.org☆11Mar 17, 2014Updated 12 years ago
- WIP open source tooling for the XC9500 / XC9500XL series of CPLDs from Xilinx.☆11Nov 5, 2021Updated 4 years ago
- A extremely size-optimized RV32I soft processor for FPGA.☆27Jun 19, 2018Updated 8 years ago
- A VHDL frontend for Yosys☆105Feb 27, 2017Updated 9 years ago
- reverse-engineering tools for FPGA bitstreams (mirrored from https://code.google.com/p/debit)☆11Mar 20, 2015Updated 11 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆31Mar 29, 2013Updated 13 years ago
- Compare HDLs☆12Feb 9, 2015Updated 11 years ago