brouhaha / xchange
Change part number or package in a Xilinx 7-series FPGA bitstream
☆36Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for xchange
- Tiny tips for Colorlight i5 FPGA board☆55Updated 3 years ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆93Updated last year
- ECP5 FPGA in an "S7 Mini" form factor☆77Updated 3 years ago
- Small footprint and configurable SPI core☆39Updated 3 weeks ago
- A wishbone controlled scope for FPGA's☆73Updated 10 months ago
- ☆43Updated last year
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆82Updated 6 years ago
- USB DFU bootloader gateware / firmware for FPGAs☆60Updated last month
- Nitro USB FPGA core☆83Updated 8 months ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆59Updated 5 years ago
- Miscellaneous ULX3S examples (advanced)☆74Updated last year
- Documenting the Anlogic FPGA bit-stream format.☆84Updated last year
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆48Updated last week
- Basic USB 1.1 Host Controller for small FPGAs☆85Updated 4 years ago
- A configurable USB 2.0 device core☆30Updated 4 years ago
- Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs☆97Updated 3 years ago
- 妖刀夢渡☆56Updated 5 years ago
- FPGA USB stack written in LiteX☆125Updated 2 years ago
- ☆20Updated 2 years ago
- ☆44Updated 2 years ago
- FPGA board-level debugging and reverse-engineering tool☆29Updated last year
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆36Updated 6 months ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆86Updated 5 years ago
- Using VexRiscv without installing Scala☆36Updated 3 years ago
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆84Updated 2 weeks ago
- PCIe adapter for an FPGA accelerator for Open CloudServer☆21Updated 4 years ago
- 🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)☆34Updated 3 years ago
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆39Updated 6 months ago
- ☆22Updated 2 years ago
- Project X-Ray Database: XC7 Series☆63Updated 2 years ago