Errare-humanum-est / HeteroGen
We solve the two challenges architects face when designing heterogeneous processors with cache coherent shared memory. First, we develop an automated tool, called HeteroGen, for composing clusters of cores, each with its own coherence protocol. Second, we show that the output of HeteroGen adheres to a precisely defined memory consistency model t…
☆15Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for HeteroGen
- agile hardware-software co-design☆46Updated 2 years ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆63Updated 5 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆53Updated last month
- EQueue Dialect☆39Updated 2 years ago
- Designing directory cache coherence protocols is complicated because coherence transactions are not atomic in modern multicore processors…☆16Updated 2 years ago
- ILA Model Database☆20Updated 4 years ago
- Artifact, reproducibility, and testing utilites for gem5☆20Updated 3 years ago
- ☆84Updated 9 months ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆30Updated 9 months ago
- HeteroCL-MLIR dialect for accelerator design☆40Updated 2 months ago
- A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.☆16Updated 2 years ago
- ordspecsim: The Swarm architecture simulator☆24Updated last year
- ☆21Updated last year
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆46Updated 4 months ago
- Heterogeneous simulator for DECADES Project☆29Updated 5 months ago
- ☆23Updated 4 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆56Updated last month
- The source code for GPGPUSim+Ramulator simulator. In this version, GPGPUSim uses Ramulator to simulate the DRAM. This simulator is used t…☆49Updated 5 years ago
- HyFiSS: A Hybrid Fidelity Stall-Aware Simulator for GPGPUs☆13Updated this week
- Domain-Specific Architecture Generator 2☆20Updated 2 years ago
- PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration☆46Updated 2 years ago
- Polyhedral High-Level Synthesis in MLIR☆29Updated last year
- CGRA framework with vectorization support.☆19Updated this week
- ☆25Updated 3 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆44Updated 2 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆38Updated last year
- A scheduler for spatial DNN accelerators that generate high-performance schedules in one shot using mixed integer programming (MIP)☆74Updated last year
- Release of stream-specialization software/hardware stack.☆116Updated last year
- ☆14Updated 2 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago