Shengrong-LSR / HDLBits-Solutions-Verilog

Related projects ⓘ

Alternatives and complementary repositories for HDLBits-Solutions-Verilog

• GuoningHuang / FPGA-CNN-accelerator-based-on-systolic-array
  2023集创赛国二，紫光同创杯。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。
  ☆122Updated 3 weeks ago
• YutongChenVictor / Fpga-accelerator-demos
  some interesting demos for starters
  ☆61Updated last year
• doveyour / mnist-nnet-hls-zynq7020-fpga
  to illustrate how to removal a Neural Network from pc to FPGA board ,it contain all the code include c code worked in pc,HLS prj acceler…
  ☆70Updated 3 years ago
• XueTianyu24 / cnn_accelerator
  【入门项目】基于PYNQ-Z2实现手写数字识别卷积神经网络硬件加速器
  ☆130Updated last year
• xddcore / OpenNNA
  一个开源的FPGA神经网络加速器。
  ☆129Updated last year
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆69Updated 2 years ago
• peilin-chen / hls_for_cnn_mnist
  【入门项目】这个仓库是用hls来实现手写数字识别CNN硬件(xilinx fpga)加速的代码
  ☆63Updated 2 years ago
• boaaaang / CNN-Implementation-in-Verilog
  Convolutional Neural Network RTL-level Design
  ☆35Updated 3 years ago
• Futuresxy / General-CNN-Accelerator
  General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。
  ☆21Updated 6 months ago
• cxlisme / FPGA-proj
  FPGA project
  ☆200Updated 2 years ago
• Xinyang-ZHANG / MNIST
  MNIST using tensorflow, c++ and fpga (zynq7010)
  ☆27Updated last year
• MasLiang / CNN-On-FPGA
  FPGA
  ☆141Updated 4 months ago
• xbdxwyh / yolov3_fpga_project
  ☆45Updated last year
• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆136Updated 9 months ago
• adamgallas / fpga_accelerator_yolov3tiny
  ☆191Updated 7 months ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆78Updated 5 months ago
• Starrynightzyq / Nexys4DDR-ARM-M3-Plate-Recognition
  车牌识别,FPGA,2019全国大学生集成电路创新创业大赛
  ☆129Updated 4 years ago
• sazczmh / PYNQ_Workshop
  ☆39Updated 5 years ago
• ChunxuGuo / SummerSchool2022
  ☆57Updated 2 years ago
• bunny965 / yolov5-fpga-hardware-acceleration
  网络训练、图像预处理以及部分hend功能是基于pc端实现的，只有主干网络部署在fpga上，片上资源无法支持整个网络所需资源，建议添加外部存储及DDR
  ☆67Updated last year
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆132Updated 2 years ago
• louisliuwei / PynqDocs
  PYNQ学习资料
  ☆159Updated 4 years ago
• Daniel-GGB / My-Digital-IC-Library
  我的数字IC厂库：Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;
  ☆67Updated 2 years ago
• tastynoob / FPGA_network
  ☆34Updated 3 years ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆93Updated 4 years ago
• OpenHEC / SNN-simulator-on-PYNQcluster
  ☆87Updated 4 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆168Updated last year
• 9334swjtu / PYNQ_softmax
  achieve softmax in PYNQ with heterogeneous computing.
  ☆61Updated 6 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆37Updated 4 years ago
• doonny / basic_knowledge
  Things to learn for new students in the Lab for AI chips and systems of BJTU .
  ☆163Updated 2 weeks ago