Alternatives and similar repositories for ysyx-npc-workbench

Users that are interested in ysyx-npc-workbench are comparing it to the libraries listed below

• yizishun / ysyx-framework
  A framework for ysyx flow
  ☆11Updated 7 months ago
• leesum1 / ysyx
  一生一芯项目
  ☆13Updated last year
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆29Updated 2 years ago
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆24Updated last month
• OSCPU / ysyxSoC
  ☆86Updated last month
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 10 months ago
• OSCPU / yosys-sta
  ☆72Updated 2 months ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆113Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆51Updated 2 years ago
• yyNoBug / RISCV-CPU
  A FPGA-supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL. Achieve good performance due to optimizations like branch p…
  ☆9Updated 5 years ago
• Groupsun / riscv-mini-five-stage
  This is my graduation project, a simple processor soft core, which implements RV32I ISA.
  ☆17Updated 6 years ago
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• MrAMS / NagiCore
  顺序单/双发射LA32R处理器 (龙芯杯2024) A LA32R CPU in chisel
  ☆20Updated 7 months ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆68Updated 2 years ago
• huangxc6 / E203_CNN_Genesys2
  Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.
  ☆19Updated last year
• zhhangBian / BOOM_chip
  乱序双发处理器，在2024年计算机系统能力大赛CPU赛道（龙芯杯）获二等奖，全国第四
  ☆14Updated 10 months ago
• Clo91eaf / PUA-MIPS
  NSCSCC 2023 The Second Prize. TEAM PUA FROM HDU.
  ☆13Updated 2 months ago
• kaitoukito / YSYX-NJU-Group
  YSYX RISC-V Project NJU Study Group
  ☆16Updated 5 months ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆171Updated 8 months ago
• KafCoppelia / uvm-mcdf
  Mirror of william_william/uvm-mcdf on Gitee
  ☆23Updated 2 years ago
• lizhirui / DreamCore
  ☆64Updated 2 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆42Updated 3 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆44Updated 4 years ago
• xiaoan109 / ysyx-workbench
  一生一芯CPU/目前做到cache/后续主要考虑ASIC DV
  ☆20Updated 5 months ago
• siyueyinghua / UVMInPracticesByZhangQiang
  《UVM实战》书本源代码和UVM 1.1d源码及Doc
  ☆38Updated 4 years ago
• CmdBlockZQG / rvcore-mini-linux
  Build mini linux for your own RISC-V emulator!
  ☆21Updated 9 months ago
• ysyx-ta / ysyx-slides
  ☆29Updated this week
• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆50Updated last week
• OSCPU / chisel-playground
  ☆68Updated 4 months ago
• puckbee / moli
  ☆15Updated last week