FPGA-Research-Manchester / fos
FOS - FPGA Operating System
☆62Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for fos
- Mathematical Functions in Verilog☆85Updated 3 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆64Updated 2 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆58Updated last month
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆80Updated 3 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆44Updated 8 years ago
- A Fast, Low-Overhead On-chip Network☆137Updated 3 weeks ago
- FuseSoC standard core library☆115Updated last month
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆79Updated last month
- ☆66Updated last year
- ☆47Updated 3 years ago
- ☆75Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆98Updated 3 years ago
- A simple DDR3 memory controller☆51Updated last year
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆47Updated this week
- Altera Advanced Synthesis Cookbook 11.0☆93Updated last year
- Python packages providing a library for Verification Stimulus and Coverage☆114Updated last month
- OPAE porting to Xilinx FPGA devices.☆38Updated 4 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆129Updated 2 weeks ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆64Updated 2 months ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆16Updated 5 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆63Updated 7 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆117Updated last year
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆110Updated 4 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆59Updated this week
- Bitstream relocation and manipulation tool.☆40Updated last year
- Fabric generator and CAD tools☆148Updated last week
- Network on Chip Implementation written in SytemVerilog☆158Updated 2 years ago
- RISC-V Verification Interface☆76Updated 2 months ago
- Ethernet interface modules for Cocotb☆56Updated last year