Alternatives and similar repositories for tinyml

Users that are interested in tinyml are comparing it to the libraries listed below

• Fraunhofer-IMS / airisc_core_complex
  Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
  ☆91Updated last year
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆72Updated 11 months ago
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆221Updated last year
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆79Updated 2 weeks ago
• gnodipac886 / ViT-FPGA-TPU
  FPGA based Vision Transformer accelerator (Harvard CS205)
  ☆122Updated 3 months ago
• Xilinx / Kria-PYNQ
  PYNQ support and examples for Kria SOMs
  ☆109Updated 9 months ago
• Xilinx / PYNQ-ZU
  PYNQ-ZU, AUP UltraScale+ MPSoC academic board
  ☆24Updated 2 weeks ago
• embedeep / FREE-TPU-V3plus-for-FPGA
  FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
  ☆146Updated last year
• Xilinx / finn-examples
  Dataflow QNN inference accelerator examples on FPGAs
  ☆217Updated 2 months ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆154Updated 5 months ago
• sumilao / Zynq-7000-DPU-TRD
  Zynq-7000 DPU TRD
  ☆45Updated 5 years ago
• Xilinx / Vitis_Embedded_Platform_Source
  ☆127Updated 6 months ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆105Updated 7 years ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆47Updated 4 years ago
• thousrm / universal_NPU-CNN_accelerator
  hardware design of universal NPU(CNN accelerator) for various convolution neural network
  ☆125Updated 3 months ago
• markcxli / FPGA_DPU
  This project is to implement YOLO v3 on Xilinx FPGA with DPU
  ☆55Updated 5 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆45Updated 2 years ago
• pulp-platform / ITA
  ☆47Updated last month
• pulp-platform / pulp-nn
  ☆81Updated last year
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆54Updated 4 years ago
• pulp-platform / pulp-sdk
  ☆111Updated last week
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆104Updated 2 years ago
• albertomarchisio / SwiftTron
  ☆44Updated 2 years ago
• AlexMontgomerie / fpgaconvnet-tutorial
  A collection of tutorials for the fpgaConvNet framework.
  ☆39Updated 8 months ago
• StefanSredojevic / Deep-Neural-Network-Hardware-Accelerator
  SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…
  ☆110Updated 5 years ago
• chrisneuf / Deep-Neural-Network-Hardware-Accelerator
  My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket
  ☆27Updated 5 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 3 years ago
• AlexMontgomerie / fpgaconvnet-hls
  ☆30Updated 6 months ago
• AlexMontgomerie / fpgaconvnet-model
  Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
  ☆29Updated 6 months ago
• hossein1387 / BARVINN
  BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
  ☆88Updated 5 months ago