Alternatives and similar repositories for ece270-simulator

Users that are interested in ece270-simulator are comparing it to the libraries listed below

• Lramseyer / vaporview
  Waveform Viewer Extension for VScode
  ☆292Updated last week
• getinstachip / vpm
  Verilog package manager written in Rust
  ☆143Updated last year
• chaseruskin / orbit
  Package manager and build system for VHDL, Verilog, and SystemVerilog
  ☆57Updated last week
• themperek / cocotb-test
  Unit testing for cocotb
  ☆165Updated last week
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆243Updated last year
• merledu / caravan
  A caravan equipped with API for creating bus protocols in Chisel with ease.
  ☆14Updated 8 months ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆472Updated last month
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆220Updated 9 months ago
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆681Updated 3 weeks ago
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆119Updated 2 months ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated last month
• librelane / librelane
  ASIC implementation flow infrastructure, successor to OpenLane
  ☆210Updated last week
• x-heep / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆232Updated this week
• Aaron-Zhao123 / ELEC50009
  Course material for ELEC50009
  ☆16Updated 10 months ago
• sscs-ose / sscs-ose-code-a-chip.github.io
  IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)
  ☆198Updated last month
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆677Updated last week
• mattvenn / awesome-opensource-asic-resources
  ☆366Updated 2 years ago
• chipsalliance / f4pga
  FOSS Flow For FPGA
  ☆415Updated 11 months ago
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆42Updated 2 years ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆192Updated last week
• zeroasiccorp / switchboard
  Communication framework for RTL simulation and emulation.
  ☆305Updated this week
• RTimothyEdwards / open_pdks
  PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…
  ☆377Updated last week
• rggen / rggen
  Code generation tool for control and status registers
  ☆435Updated 2 weeks ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆489Updated this week
• zaellis / continue_with_sv
  Software and resources to help Purdue students (and others) continue developing with SystemVerilog after losing access to proprietary too…
  ☆16Updated 4 years ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆185Updated 2 weeks ago
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆124Updated 2 years ago
• raysalemi / Python4RTLVerification
  ☆170Updated 3 years ago
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆65Updated 2 months ago
• TheClams / SystemVerilog
  SystemVerilog plugin for Sublime Text
  ☆49Updated 2 months ago