Alternatives and similar repositories for simple_cache_sim

Users that are interested in simple_cache_sim are comparing it to the libraries listed below

• bol-edu / course-lab_1
  Board: PYNQ-Z2, Vitis version: 2022.1
  ☆21Updated last year
• arm-university / Modern-System-on-Chip-Design-on-Arm
  A textbook on system on chip design using Arm Cortex-A
  ☆40Updated 6 months ago
• darchr / dram-cache-model
  This is where gem5 based DRAM cache models live.
  ☆18Updated 2 years ago
• seifhelal / Cache-Simulator
  A cache simulator, using the C++ language, to simulate a direct-mapped, fully associative and set-associative cache. It has a set of memo…
  ☆22Updated 8 years ago
• accomdemy / accomdemy_rv32i
  伴伴學 RISC-V RV32I Architecture CPU
  ☆31Updated 3 years ago
• MPSLab-ASU / ML-Accelerators
  Topics in Machine Learning Accelerator Design
  ☆90Updated 2 years ago
• ucb-eecs251b / sp22-labs
  Contains all labs for EECS 251B for spring 2022
  ☆12Updated 3 years ago
• NamanMakkar / ECE5545-ML-Hardware-Systems
  This repo contains the Assignments from Cornell Tech's ECE 5545 - Machine Learning Hardware and Systems offered in Spring 2023
  ☆40Updated 2 years ago
• Xilinx / xup_aie_training
  Hands-on experience programming AI Engines using Vitis Unified Software Platform
  ☆40Updated last year
• ys1998 / spsim
  Simulator for a superscalar processor with dynamic scheduling and branch prediction
  ☆15Updated 7 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆217Updated last month
• gem5bootcamp / gem5-bootcamp-env
  The gem5 Bootcamp 2022 environment. Archived.
  ☆36Updated last year
• AleksandarKostovic / SystemC-tutorial
  Brief SystemC getting started tutorial
  ☆95Updated 6 years ago
• 0xd3ba / build-your-own-prefetcher
  This repository is meant to be a guide for building your own prefetcher for CPU caches and evaluating it, using ChampSim simulator
  ☆44Updated 3 years ago
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆68Updated 2 weeks ago
• EECS150 / fpga_project_skeleton_fa22
  ☆17Updated last year
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆125Updated last year
• CMU-SAFARI / PiDRAM
  PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …
  ☆71Updated 2 years ago
• toddmaustin / simplesim-3.0
  SimpleScalar version 3.0 (official repository)
  ☆54Updated 2 years ago
• learnwithexamples / learnsystemc
  Learn systemC with examples
  ☆125Updated 3 years ago
• greati / processor_risc
  A simple processor implemented in SystemC
  ☆26Updated 9 years ago
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆34Updated 5 years ago
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆76Updated 3 months ago
• vortexgpgpu / vortex_tutorials
  ☆204Updated last month
• dcblack / ModernSystemC
  Example code for Modern SystemC using Modern C++
  ☆69Updated 3 years ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆150Updated 2 years ago
• tukl-msd / DRAMSys
  DRAMSys a SystemC TLM-2.0 based DRAM simulator.
  ☆325Updated last week
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆15Updated 3 years ago
• Accelergy-Project / timeloop-accelergy-exercises
  Exercises for exploring the Fibertree, Timeloop and Accelergy tools
  ☆110Updated 8 months ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆151Updated 6 years ago