Alternatives and similar repositories for uvm_agents

Users that are interested in uvm_agents are comparing it to the libraries listed below

• amiq-consulting / amiq_apb
  SystemVerilog VIP for AMBA APB protocol
  ☆82Updated 4 years ago
• hjking / uvm_gen
  UVM Generator
  ☆48Updated last year
• VerificationExcellence / SystemVerilogAssertions
  Examples and reference for System Verilog Assertions
  ☆89Updated 8 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆56Updated 8 years ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆152Updated 6 months ago
• amiq-consulting / svaunit
  SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  ☆74Updated 4 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆77Updated 5 years ago
• cluelogic / cluelib
  A generic class library in SystemVerilog
  ☆86Updated 4 years ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆157Updated 5 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆153Updated 7 years ago
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆147Updated 4 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆90Updated 3 months ago
• andres-mancera / ethernet_10ge_mac_SV_tb
  SystemVerilog testbench for an Ethernet 10GE MAC core
  ☆46Updated 9 years ago
• kaushalmodi / custom_uvm_report_server
  Customized UVM Report Server
  ☆42Updated 5 years ago
• luuvish / amba3-vip
  amba3 apb/axi vip
  ☆51Updated 10 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆135Updated 8 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆114Updated last year
• yuravg / uvm_tb_cross_bar
  SystemVerilog UVM testbench example
  ☆37Updated last year
• naragece / uvm-testbench-tutorial-simple-adder
  A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology
  ☆114Updated 11 years ago
• accellera / uvm
  ☆57Updated 9 years ago
• akzare / Async_FIFO_Verification
  Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.
  ☆58Updated 5 years ago
• nelsoncsc / ISP_UVM
  A Framework for Design and Verification of Image Processing Applications using UVM
  ☆116Updated 8 years ago
• zhajio1988 / YASA
  Yet Another Simulation Architecture
  ☆78Updated 5 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆73Updated 5 years ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆38Updated 5 years ago
• Anjali-287 / SPI-Interface
  UVM Testbench to verify serial transmission of data between SPI master and slave
  ☆54Updated 5 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆51Updated 6 years ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆50Updated 4 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆161Updated 3 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆212Updated 5 years ago