Alternatives and similar repositories for rowhammer_armv8

Users that are interested in rowhammer_armv8 are comparing it to the libraries listed below

• flowyroll / medusa
  Medusa Repository: Transynther tool and Medusa Attack
  ☆23Updated 5 years ago
• cgvwzq / evsets
  Tool for testing and finding minimal eviction sets
  ☆105Updated 4 years ago
• flowyroll / uarchsec
  ☆46Updated 6 years ago
• vusec / tlbdr
  ☆18Updated 3 years ago
• cgvwzq / cachequery
  HW interface for memory caches
  ☆28Updated 5 years ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆73Updated 7 months ago
• ECLab-ITU / Cache-Side-Channel-Attacks
  This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.
  ☆56Updated 6 years ago
• KULeuven-COSIC / PRIME-SCOPE
  The open-source component of Prime+Scope, published at CCS 2021
  ☆35Updated 2 years ago
• isec-tugraz / transientfail
  Website and PoC collection for transient execution attacks
  ☆189Updated last year
• libtea / frameworks
  Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser
  ☆62Updated 3 years ago
• vernamlab / medusa
  Medusa Repository: Transynther tool and Medusa Attack
  ☆19Updated 5 years ago
• CPU-Security / Spectre-V4-ng
  The code in this project demonstrates 2 novel Spectre-V4 attacks, named as out-of-place Spectre-STL and Spectre-CTL, based on the Specula…
  ☆22Updated last year
• nepoche / Flush-Reload
  A flush-reload side channel attack implementation
  ☆54Updated 3 years ago
• googleinterns / hw-fuzzing
  ☆87Updated 2 years ago
• zzrcxb / LLCFeasible
  Open-source release of "Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud" (ASPLOS '24)
  ☆27Updated 7 months ago
• renxida / iseedeaduops-poc
  Proof-of-concept for I See Dead Micro-Ops transient execution attack
  ☆14Updated 3 years ago
• saiteja-talluri / Microarchitectural-attacks
  Implementation of flush + reload attack to extract private key from the GnuPG implementation of RSA.
  ☆11Updated 6 years ago
• isec-tugraz / halfdouble
  ☆16Updated 3 years ago
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 7 years ago
• amdprefetch / amd-prefetch-attacks
  ☆27Updated last year
• gururaj-s / streamline
  Streamline Covert Channel Attack (presented in ASPLOS'21)
  ☆20Updated 4 years ago
• cispa / osiris
  Proof-of-concept implementation for the paper "Osiris: Automated Discovery of Microarchitectural Side Channels" (USENIX Security'21)
  ☆60Updated 4 months ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated last month
• pierreay / reproduce-spectre-gem5
  Repository of the paper "Reproducing Spectre Attack with gem5, How To Do It Right?"
  ☆17Updated 2 years ago
• vusec / xlate
  Code to evaluate XLATE attacks as well existing cache attacks.
  ☆31Updated 7 years ago
• compsec-snu / difuzz-rtl
  ☆97Updated last year
• FPSG-UIUC / Peek-a-Walk
  Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"
  ☆28Updated 3 months ago
• isec-tugraz / cache_template_attacks
  This repository contains several tools to perform Cache Template Attacks
  ☆157Updated 3 weeks ago
• comsec-group / cascade-artifacts
  Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)
  ☆136Updated last year
• Fraunhofer-AISEC / archie
  ARCHIE is a QEMU-based architecture-independent fault evaluation tool, that is able to simulate transient and permanent instruction and d…
  ☆26Updated this week