Alternatives and similar repositories for CSE240A

Users that are interested in CSE240A are comparing it to the libraries listed below

• eisl-nctu / falco
  A 32-bit out-of-order RISC-V superscalar for Xilinx FPGAs.
  ☆16Updated 3 years ago
• pulp-platform / rbe
  Reconfigurable Binary Engine
  ☆17Updated 4 years ago
• Risto97 / systemc_uvm_verilator
  ☆12Updated 3 years ago
• CESNET / sphinx-vhdl
  ☆23Updated 5 months ago
• pulp-platform / hwpe-mac-engine
  An example Hardware Processing Engine
  ☆11Updated 2 years ago
• paradigm-works / uvmtb_template
  Simple UVM testbench development using the uvmtb_template files
  ☆16Updated 7 months ago
• sheldonucr / ucr-eecs168-lab
  The lab schedules for EECS168 at UC Riverside
  ☆486Updated 11 months ago
• smartfoxdata / uvm_apb
  uvm_apb is a uvm package for modeling and verifying APB (Advanced Periperal Bus) protocol
  ☆20Updated 7 months ago
• vignesh-raghavan / AES128
  Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.
  ☆17Updated 7 years ago
• Muriukidavid / systemc-examples
  A repository for SystemC Learning examples
  ☆70Updated 2 years ago
• BalaDhinesh / Accelerating_Standard_and_Modified_AES128
  Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms
  ☆31Updated 3 years ago
• IamFlea / AdderCircuitGenerator
  This script generates and analyzes prefix tree adders.
  ☆39Updated 4 years ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆17Updated last year
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆33Updated 3 months ago
• tomtor / HDL-deflate
  FPGA implementation of deflate (de)compress RFC 1950/1951
  ☆62Updated 6 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• pulp-platform / hwpe-stream
  IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
  ☆20Updated last week
• mbgh / aes128-hdl
  A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.
  ☆40Updated 10 years ago
• pulp-platform / axi_node
  AXI X-Bar
  ☆19Updated 5 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆76Updated 4 years ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆97Updated 2 months ago
• jwwebbopen / VerilogTools
  Tools for Verilog HDL development.
  ☆10Updated 13 years ago
• Freecellera / freecellera-uvm
  Freecellera fork of the Universal Verification Methodology (SystemVerilog verification library from Accellera.org)
  ☆11Updated 10 years ago
• sgherbst / anasymod
  A framework for FPGA emulation of mixed-signal systems
  ☆36Updated 4 years ago
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆26Updated 5 years ago
• vsdip / avsddac_3v3_sky130_v2
  ☆16Updated 2 years ago
• suoto / hdl_string_format
  VHDL package to provide C-like string formatting
  ☆15Updated 3 years ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆46Updated 4 years ago
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆53Updated last year
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆43Updated 5 years ago