Alternatives and similar repositories for spi_avip

Users that are interested in spi_avip are comparing it to the libraries listed below

• muneeb-mbytes / i2c_avip
  I2C Accelerated VIP
  ☆14Updated last year
• muneeb-mbytes / uart_avip
  UART Accelerated VIP
  ☆13Updated 3 years ago
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆104Updated 2 years ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆156Updated 7 months ago
• mbits-mirafra / linux_course
  This course walks you through the Linux OS commands and usage.
  ☆19Updated 3 years ago
• hanysalah / uart2bustestbench
  UVM Verification IP to uart2bus IP.
  ☆23Updated 3 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆136Updated 8 years ago
• JoseIuri / UVM-APB_RAL
  This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
  ☆48Updated 5 years ago
• Lampro-Mellon / apb-uart-uvm-env
  ☆48Updated 2 years ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆160Updated 5 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆163Updated 3 years ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆51Updated 4 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆93Updated 4 months ago
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆149Updated 4 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆118Updated last year
• muneeb-mbytes / pulpino__spi_master__ip_verification
  To verify the SPI Master IP using the APB and SPI AVIPs
  ☆20Updated 3 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆160Updated 7 years ago
• Anjali-287 / SPI-Interface
  UVM Testbench to verify serial transmission of data between SPI master and slave
  ☆54Updated 5 years ago
• amiq-consulting / amiq_apb
  SystemVerilog VIP for AMBA APB protocol
  ☆86Updated 4 years ago
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆30Updated 3 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆216Updated 5 years ago
• VimfulDang / APB-SPI-Controller-Verification
  UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC2…
  ☆15Updated last year
• Mohamed-Younis / SPI-UVM-Testbench
  ☆24Updated 4 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆75Updated 5 years ago
• muneeb-mbytes / axi4_avip
  Development of AXI4 Accelerated VIP
  ☆32Updated 2 years ago
• akzare / Async_FIFO_Verification
  Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.
  ☆59Updated 5 years ago
• Kholoud-Ebrahim / SPI_Protocol
  UVM based Verification of SPI_Protocol. A Serial intra System Communication Peripheral Protocol.
  ☆10Updated 2 years ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆38Updated 5 years ago
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆65Updated 2 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆191Updated 7 years ago