lulinchen / FPGA_CryptoNight_V7Links
FPGA CryptoNight V7 Minner
☆31Updated 6 years ago
Alternatives and similar repositories for FPGA_CryptoNight_V7
Users that are interested in FPGA_CryptoNight_V7 are comparing it to the libraries listed below
Sorting:
- Simple mono FM Radio.☆49Updated 9 years ago
- FPGA core boards / evaluation boards based on CDCTL hardware☆93Updated 4 years ago
- USB Full Speed PHY☆48Updated 5 years ago
- 蚂蚁S9矿板移植pynq2.5☆36Updated 5 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆29Updated 2 years ago
- Digilent JTAG clone hardware + eeprom firmware (.bin)☆71Updated 3 years ago
- PulseRain FP51 MCU, with peripherals☆17Updated 7 years ago
- USB-PD-3.1-Verilog☆16Updated last year
- USB serial device (CDC-ACM)☆42Updated 5 years ago
- Deprecated, no longer updated, please change to https://www.nucleisys.com/index.php☆25Updated 4 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆18Updated 7 years ago
- GoAI 2.0 Public Repository☆25Updated 3 years ago
- USB 2.0 Device IP Core☆72Updated 8 years ago
- EBAZ4205 is Xilinx Zynq based mining board used in Ebang Ebit E9+ bitcoin miner machine.☆89Updated last year
- Experimental development board interfacing Xilinx Kintex-7 FPGA with LPDDR4 SDRAM☆39Updated last year
- turbo 8051☆29Updated 8 years ago
- ☆18Updated 7 years ago
- Verilog UART FIFO that will just echo back characters. Useful for testing the communications path.☆13Updated 10 years ago
- ESP8266 Xilinx Virtual Cable - wifi JTAG☆40Updated 4 years ago
- ☆79Updated 6 years ago
- FT2232HL JTAG & UART Downloader☆20Updated 4 years ago
- Communication channel from FPGA (Alterra EP4CE10) and Linux (Lichee PI Allwinner V3S)☆28Updated 5 years ago
- Bitcoin miner for Xilinx FPGAs☆99Updated 12 years ago
- High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.☆29Updated 9 years ago
- Schematics and sample projects for S9 antminer control board sold as development board☆102Updated 5 years ago
- 🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.☆25Updated 3 years ago
- My self-designed ZYNQ-7010 4-layer developement board.☆33Updated 4 years ago
- USB 1.1 PHY☆11Updated 11 years ago
- ULPI Link Wrapper (USB Phy Interface)☆33Updated 5 years ago
- Wireless JTAG 'cable' for Xilinx FPGAs. This is an 'English fork' of https://github.com/ciniml/xvc-esp32 project.☆125Updated 4 years ago