Alternatives and similar repositories for manticore

Users that are interested in manticore are comparing it to the libraries listed below

• keystone-enclave / riscv-pk
  Security monitor for Keystone Enclave (mirror of riscv-pk). Will be deprecated when openSBI port is ready
  ☆35Updated 4 years ago
• rems-project / isla
  Symbolic execution tool for Sail ISA specifications
  ☆78Updated 3 weeks ago
• maerhart / llhd
  A low-level intermediate representation for hardware description languages
  ☆28Updated 5 years ago
• phayes / sidefuzz
  Fuzzer to automatically find side-channel (timing) vulnerabilities
  ☆121Updated 4 years ago
• isec-tugraz / memsec
  Framework for building transparent memory encryption and authentication solutions
  ☆27Updated 7 years ago
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆41Updated 11 months ago
• diodesign / diosix
  A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V
  ☆198Updated 9 months ago
• rust-vmm / vm-fdt
  ☆18Updated last year
• 0xADE1A1DE / CryptOpt
  CryptOpt: Verified Compilation with Randomized Program Search for Cryptographic Primitives
  ☆62Updated last year
• proteus-core / prospect
  ProSpeCT: Provably Secure Speculation for the Constant-Time Policy.
  ☆19Updated last month
• rems-project / sail-arm
  Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model
  ☆88Updated 3 months ago
• chipsalliance / caliptra-mcu-sw
  Caliptra MCU Software
  ☆20Updated this week
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆64Updated 2 months ago
• rivosinc / salus
  Risc-V hypervisor for TEE development
  ☆122Updated 3 months ago
• rvkrypto / rvkrypto-fips
  [HISTORICAL] FIPS and higher-level algorithm tests for RISC-V Crypto Extension
  ☆28Updated last year
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆46Updated last month
• CTSRD-CHERI / qemu
  QEMU with support for CHERI
  ☆59Updated this week
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆60Updated this week
• scarv / xcrypto
  XCrypto: a cryptographic ISE for RISC-V
  ☆93Updated 2 years ago
• riscv / riscv-cfi
  This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …
  ☆92Updated this week
• uw-unsat / jitterbug
  Verification of BPF JIT compilers
  ☆56Updated 2 years ago
• rems-project / rmem
  rmem public repo
  ☆48Updated 4 months ago
• elliottt / easy-smt
  Easy SMT solver interaction
  ☆35Updated 2 months ago
• fintelia / riscv-decode
  Simple library for decoding RISC-V instructions
  ☆24Updated last month
• lamps-wg / dilithium-certificates
  I-D that describes the algorithm identifiers for NIST's PQC ML-DSA for use in the Internet X.509 Public Key Infrastructure
  ☆13Updated this week
• riscv / riscv-cheri
  This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory prot…
  ☆81Updated this week
• scaspin / memory-safe-assembly
  Bottom-up memory-safety for assembly language using symbolic execution
  ☆15Updated 3 weeks ago
• IBM / ACE-RISCV
  Assured confidential execution (ACE) implements VM-based trusted execution environment (TEE) for embedded RISC-V systems with focus on a …
  ☆191Updated this week
• chipsalliance / caliptra-sw
  Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
  ☆127Updated this week
• CharlyCst / miralis
  Miralis is a RISC-V firmware that virtualizes RISC-V firmware
  ☆35Updated last month