kostis / ntua_compilersLinks
Programs and utilities for the Compilers course at NTUA
☆18Updated 3 weeks ago
Alternatives and similar repositories for ntua_compilers
Users that are interested in ntua_compilers are comparing it to the libraries listed below
Sorting:
- 3-wide superscalar, out-of-order RISC-V processor (RV32IM subset) in System Verilog, demonstrating key Instruction-Level Parallelism☆23Updated 5 months ago
- A collection of Matplotlib and Seaborn recipes and utilities collected over years of colorful plot-making☆22Updated 2 years ago
- ☆18Updated last year
- risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom☆15Updated 5 years ago
- RARS -- RISC-V Assembler and Runtime Simulator☆1,497Updated last year
- Championship Branch Prediction 2025☆67Updated 8 months ago
- Perceptron-based branch predictor written in C++☆12Updated 9 years ago
- ☆40Updated 2 months ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆161Updated this week
- FPGA routing delay sensors for effective remote power analysis attacks☆13Updated last year
- ☆35Updated 2 years ago
- PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.☆28Updated last month
- ☆1,117Updated 2 weeks ago
- A modified version of McPAT for the COSSIM framework. The code is based on McPAT v1.3 and integrates with cgem5.☆17Updated 3 years ago
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆92Updated 3 months ago
- Lab Material for CAE☆44Updated last month
- RISC-V instruction set simulator built for education☆221Updated 3 years ago
- Source Code for training and evaluating BranchNet models for branch prediction☆41Updated 5 years ago
- An rv32i inspired ISA, SIMT GPU implementation in system-verilog.☆222Updated 11 months ago
- Sail RISC-V model☆667Updated this week
- Installs Vivado on M1/M2/M3 macs☆514Updated last year
- ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture …☆669Updated last week
- Learn how to build our own RV32I(M) core, verify it and actually use it. From scratch & with more than 200 pages of detailed tutorial wit…☆354Updated 2 weeks ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆160Updated 5 years ago
- Extendable Translating Instruction Set Simulator☆40Updated 2 weeks ago
- RISC-V Assembly code assembler package for Python.☆53Updated 2 years ago
- An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model☆528Updated last year
- risc-v single cycle implementation☆20Updated 4 years ago
- Parametric NTT/INTT Hardware Generator☆80Updated 4 years ago
- The OpenPiton Platform☆766Updated 4 months ago