Alternatives and similar repositories for ntua_compilers

Users that are interested in ntua_compilers are comparing it to the libraries listed below

• 0BAB1 / HOLY_CORE_COURSE
  Learn how to build our own RV32I core, verify it and actually use it. From scratch & with more than 200 pages of detailed tutorial with s…
  ☆195Updated this week
• gsarkis / tikz-mux
  A multiplexer for TikZ Circuits
  ☆14Updated 9 years ago
• simon-staal / Odyssey_C_Compiler
  This repository contains the preprocessed C90 to MIPS assembly compiler produced as part of the EIE 2nd Year Instruction Set Architecture…
  ☆18Updated 2 years ago
• chaseruskin / orbit
  Package manager and build system for VHDL, Verilog, and SystemVerilog
  ☆48Updated 2 weeks ago
• jackodirks / AXI4_Master
  A VHDL implementation of an AXI4 Master
  ☆15Updated 7 years ago
• arhamhashmi01 / Axi4-lite
  This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codeba…
  ☆11Updated last year
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆192Updated 3 years ago
• CuetoA / Plantilla-Protocolo-de-investigacion
  Plantilla generada para la creación de un Protocolo de investigación con formato IEEE
  ☆8Updated 3 years ago
• ghdl / ghdl
  VHDL 2008/93/87 simulator
  ☆2,597Updated this week
• Digilent / digilent-xdc
  A collection of Master XDC files for Digilent FPGA and Zynq boards.
  ☆600Updated 8 months ago
• dharmx / walls
  All of my wallpapers in one repo.
  ☆3,527Updated last year
• b0-n0-b0 / Computer-Engineering
  UNIPI Computer Engineering github: a collection of utilities and infos about all the exams
  ☆35Updated 3 weeks ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆202Updated 4 months ago
• fabriziotappero / Free-Range-VHDL-book
  Latex source files of the open-source book FREE RANGE VHDL
  ☆298Updated 4 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆143Updated this week
• AntonovAlexander / activecore
  Hardware generation library based on "Kernel IP" (KIP) cores: programmable execution kernels inferred from microarchitectural templates
  ☆28Updated 5 months ago
• johnwinans / rvalp
  RISC-V Assembly Language Programming
  ☆235Updated 11 months ago
• TheThirdOne / rars
  RARS -- RISC-V Assembler and Runtime Simulator
  ☆1,374Updated last year
• tscheipel / HaDes-V
  HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…
  ☆74Updated last month
• veryl-lang / veryl
  Veryl: A Modern Hardware Description Language
  ☆746Updated this week
• ARC-Lab-UF / intel-training-modules
  ☆42Updated 2 years ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆143Updated this week
• sunmagnetics / RSFQlib
  RSFQ cell library
  ☆39Updated 2 years ago
• stevehoover / LF-Building-a-RISC-V-CPU-Core
  ☆398Updated 4 months ago
• calyxir / calyx
  Intermediate Language (IL) for Hardware Accelerator Generators
  ☆540Updated this week
• togulcan / TUM-SystemClab
  TUM EI7402 SystemC laboratory assignments
  ☆10Updated 3 years ago
• kcelebi / riscv-assembler
  RISC-V Assembly code assembler package for Python.
  ☆52Updated 2 years ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆115Updated 4 years ago
• riscv / sail-riscv
  Sail RISC-V model
  ☆575Updated this week
• goossens-springer / goossens-book-ip-projects
  this repository contains all the ip projects presented in the HLS/RISC-V/Computer Architecture book written by Goossens and published by …
  ☆25Updated 9 months ago