Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"
☆31Dec 10, 2021Updated 4 years ago
Alternatives and similar repositories for DRFM
Users that are interested in DRFM are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- UESTC-雷达信号产生与处理的设计与验证☆19Jun 6, 2019Updated 6 years ago
- Design, fabrication, and assembly files for CMOS imaging sensor PCB☆15Mar 16, 2017Updated 9 years ago
- development interface mil-std-1553b for system on chip☆24Feb 2, 2018Updated 8 years ago
- High-througput logic analyzer for FPGA☆16Oct 8, 2020Updated 5 years ago
- Miniature 8GHz FMCW Radar☆12Mar 29, 2016Updated 10 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- 雷达信号分选任务是对雷达脉冲序列进行K-means聚类,以判定每个脉冲的所属雷达 1、对 2GHz 以内的信号进行多项滤波,以确定信号的中心频带 2、构建分选数据集,对场景中雷达脉冲序列信号进行仿真,并通过UDP传至开发处理 3、基于C++实现K-means算法并部署…☆21Aug 17, 2023Updated 2 years ago
- This repository contains FPGA/HDL demonstrations several beamforming and radar designs. Simulink models and MATLAB reference code are pro…☆79Jul 26, 2023Updated 2 years ago
- Public repository of the data, scripts and methodology presented in the paper "Towards On-Board SAR Processing with FPGA Accelerators and…☆13Apr 12, 2023Updated 3 years ago
- User Space NVMe Driver (modified for use on Zynq UltraScale+ MPSoC)☆11Sep 26, 2018Updated 7 years ago
- Xilinx IP repository☆13May 5, 2018Updated 7 years ago
- Verilog implementation of a ultrasonic radar☆19Jan 7, 2018Updated 8 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆59Jan 28, 2026Updated 2 months ago
- VHDL PCIe Transceiver☆33Jul 2, 2020Updated 5 years ago
- Simple KMDF example driver, used as a case study in our WDF seminar.☆11Jun 16, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆34Jan 2, 2024Updated 2 years ago
- Documents and software for the polyphase filter bank that receives Phase 4 Ground uplink signals.☆20Jun 6, 2019Updated 6 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 7 years ago
- Final Year thesis project 2014. Investigating Passive Radar detection methods and implementing a new algorithm, Range-Doppler transformat…☆35Nov 9, 2014Updated 11 years ago
- ☆21Dec 9, 2018Updated 7 years ago
- IP Catalog for Raptor.☆18Dec 6, 2024Updated last year
- ☆24Aug 26, 2017Updated 8 years ago
- Velocity Measurement by Doppler Radar implemented on Matlab☆12Nov 24, 2017Updated 8 years ago
- 通过SPI协议实现FPGA multiboot在线升级功能☆13May 17, 2018Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆19Sep 15, 2021Updated 4 years ago
- MIL-STD-1553 <-> SPI bridge☆31Sep 4, 2018Updated 7 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Mar 6, 2018Updated 8 years ago
- CAN 2.0B Controller in VHDL and Verilog☆11Nov 22, 2023Updated 2 years ago
- Professor: C.H. Yang☆10Aug 16, 2025Updated 7 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆70Apr 7, 2026Updated last week
- IP prototyping in FPGA hardware☆18Aug 28, 2018Updated 7 years ago
- A curated list of FMCW-LiDAR papers and resources.☆39Mar 12, 2026Updated last month
- Vivado project for Xilinx Artix FPGA, used in logic analyzer☆13Jul 16, 2021Updated 4 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Hardware monorepo avionics PCB☆13Updated this week
- 10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL☆26Jan 28, 2025Updated last year
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆41Feb 24, 2025Updated last year
- ☆21Jul 28, 2021Updated 4 years ago
- Signal Process&&Communicate System☆46Jan 3, 2022Updated 4 years ago
- Robust CFAR detector based on censored harmonic averaging☆11Sep 1, 2023Updated 2 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆17Mar 15, 2018Updated 8 years ago