greati / processor_risc
A simple processor implemented in SystemC
☆24Updated 8 years ago
Alternatives and similar repositories for processor_risc:
Users that are interested in processor_risc are comparing it to the libraries listed below
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆56Updated last week
- SystemC training aimed at TLM.☆27Updated 4 years ago
- A repository for SystemC Learning examples☆66Updated 2 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 3 years ago
- Tests for example Rocket Custom Coprocessors☆70Updated 5 years ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆102Updated last week
- CVA6 SDK containing RISC-V tools and Buildroot☆61Updated 8 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆60Updated 6 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆37Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated 2 weeks ago
- Archives of SystemC from The Ground Up Book Exercises☆30Updated 2 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆48Updated 7 years ago
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- Platform Level Interrupt Controller☆36Updated 9 months ago
- Pure digital components of a UCIe controller☆55Updated this week
- Basic floating-point components for RISC-V processors☆64Updated 5 years ago
- Advanced Architecture Labs with CVA6☆54Updated last year
- Development of a Network on Chip Simulation using SystemC.☆31Updated 7 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 3 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆64Updated last month
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆21Updated 6 years ago
- Learn systemC with examples☆108Updated 2 years ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆25Updated 5 months ago
- HLS for Networks-on-Chip☆33Updated 4 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆44Updated 4 months ago
- Network on Chip Implementation written in SytemVerilog☆168Updated 2 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 9 months ago
- Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 models☆16Updated 11 years ago