hellollvm / nanpanjiang-projectLinks
由HelloLLVM社区主席邱吉博士发起,联合HelloGCC等技术社区,推出了「南盘江计划」,致力于帮助更多的女性工程师在编译等基础软件领域实现个人职业目标。
☆40Updated 7 months ago
Alternatives and similar repositories for nanpanjiang-project
Users that are interested in nanpanjiang-project are comparing it to the libraries listed below
Sorting:
- PLCT实验室的 RISC-V V Spec 实现,基于llvm/llvm-project,rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8☆161Updated 5 months ago
- Yet another toy CPU.☆92Updated 2 years ago
- ChocoPy LLVM Repo☆79Updated 3 years ago
- This is a tutorial to learn LLVM, I realize a backend to compiler machine code for cpu0 which is a simple RISC cpu.☆270Updated 4 years ago
- 《自己动手写AI编译器》☆33Updated last year
- 方舟编译入门技术课程的 配套代码☆30Updated 5 years ago
- ☆98Updated last year
- Learn how to write a minimal working linker from scratch☆109Updated last year
- compilerbook☆52Updated 4 years ago
- 《从零开始的RISC-V模拟器开发》配套的PPT和教学资料☆234Updated 4 years ago
- A simple and fast RISC-V JIT emulator.☆156Updated last year
- learn javassist by example☆30Updated 4 years ago
- Getting Started with LLVM Core Libraries (中文版),翻译:潘立丰☆138Updated 2 years ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆38Updated 3 years ago
- 平头哥玄铁C910的LLVM工具链支持,由PLCT实验室提供,非官方版本☆76Updated 4 years ago
- 《LLVM Techniques, Tips, and Best Practices》的非专业个人翻译☆135Updated 4 years ago
- This repo stores a more profound view of Computer Architecture: A Quantitative Approach that tells multi-tenancy, virtualize, fine graine…☆29Updated last month
- LLVM OpenCL C compiler suite for ventus GPGPU☆58Updated last month
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- Super fast RISC-V ISA emulator for XiangShan processor☆309Updated last week
- 本课程基于Rui的chibicc,@sunshaoce 和@ksco将其由原来的X86架构改写为RISC-V 64架构,同时加入了大量的中文注释,并且配有316节对应于每一个commit的课程,帮助读者可以层层推进、逐步深入的学习编译器的构造。☆361Updated 2 years ago
- Here is a final lab of Compiler in USTC, focusing on MLIR☆20Updated 5 years ago
- 图书《深入理解LLVM代码生成》的配套示例代码☆40Updated last year
- My First Language Frontend with LLVM Tutorial in Chinese☆79Updated 2 years ago
- 💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…☆206Updated 5 years ago
- 《Learn LLVM 17》的非专业个人翻译☆156Updated last year
- CPU micro benchmarks☆76Updated 3 weeks ago
- My knowledge base☆78Updated this week
- LLVM Backend tutorial Cpu0☆26Updated 2 years ago
- An unofficial reference implementation of the C Minus Minus Compiler☆70Updated last year