Alternatives and similar repositories for tools-cocotb-verilator-build:

Users that are interested in tools-cocotb-verilator-build are comparing it to the libraries listed below

• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆17Updated last year
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated last week
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆31Updated 6 months ago
• SymbioticEDA / getting-started-FV
  ☆18Updated 4 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆25Updated last week
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 8 years ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated last month
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• PeterMonsson / sv_waveterm
  ☆9Updated last year
• enjoy-digital / litesata_axiom
  ☆12Updated 3 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• shalan / Chameleon_SoC
  AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...
  ☆12Updated 4 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆24Updated last year
• ieee-ceda-datc / datc-rdf-calibrations
  ☆17Updated 2 months ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆16Updated 8 months ago
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆24Updated 8 months ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆9Updated 4 years ago
• rdiez / jtag_dpi
  JTAG DPI module for OpenRISC simulation with Verilator
  ☆17Updated 12 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆26Updated 10 months ago
• wallento / cocotbext-wishbone
  ☆13Updated last month
• freecores / sgmii
  SGMII
  ☆10Updated 10 years ago
• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆24Updated last year
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆36Updated 4 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 6 months ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago