Alternatives and similar repositories for riscv-llvm:

Users that are interested in riscv-llvm are comparing it to the libraries listed below

• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 5 years ago
• ccelio / riscv-boom-doc
  Documentation for the BOOM processor
  ☆47Updated 7 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• riscv / riscv-CMOs
  ☆85Updated 2 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆139Updated last week
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆52Updated 4 years ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• riscvarchive / riscv-fesvr
  RISC-V Frontend Server
  ☆62Updated 5 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆154Updated 4 years ago
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆85Updated 2 years ago
• tvanas / r-vex
  A reconfigurable and extensible VLIW processor implemented in VHDL
  ☆32Updated 9 years ago
• scale-lab / la-core
  Linear algebra accelerators for RISC-V (published in ICCD 17)
  ☆66Updated 7 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• ucb-bar / sha3
  ☆78Updated last year
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆94Updated 3 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆83Updated 3 years ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 7 years ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆74Updated last year
• riscv / riscv-aclint
  ☆42Updated 3 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆168Updated 7 months ago
• esperantotech / boom-template
  A template for building new projects/platforms using the BOOM core.
  ☆24Updated 6 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated 11 months ago
• riscv-boom / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆40Updated 5 years ago
• CTSRD-CHERI / SIMTight
  Synthesisable SIMT-style RISC-V GPGPU
  ☆32Updated 2 weeks ago
• riscv / riscv-test-env
  ☆45Updated 2 months ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆148Updated 2 years ago
• mrc-donato / CHIPKIT-Tutorial
  ☆15Updated 4 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆73Updated 6 months ago