andestech / riscv-llvmLinks
☆14Updated 8 years ago
Alternatives and similar repositories for riscv-llvm
Users that are interested in riscv-llvm are comparing it to the libraries listed below
Sorting:
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago
- RISC-V GPGPU☆35Updated 5 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆149Updated 2 weeks ago
- A template for building new projects/platforms using the BOOM core.☆24Updated 6 years ago
- Documentation for the BOOM processor☆47Updated 8 years ago
- Original RISC-V 1.0 implementation. Not supported.☆42Updated 7 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆165Updated 5 years ago
- ☆89Updated 3 months ago
- ☆50Updated 2 months ago
- ☆88Updated 2 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆162Updated 3 years ago
- The Shang high-level synthesis framework☆120Updated 11 years ago
- ☆61Updated 4 years ago
- Synthesisable SIMT-style RISC-V GPGPU☆44Updated 4 months ago
- Workshop on Computer Architecture Research with RISC-V (CARRV)☆41Updated last year
- A Simple As Possible RISCV-32I core with debug module.☆42Updated 5 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆67Updated 8 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆179Updated 6 months ago
- OmniXtend cache coherence protocol☆82Updated 5 months ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆126Updated last year
- A parallel and distributed simulator for thousand-core chips☆26Updated 7 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- ☆81Updated last year
- ☆110Updated 7 years ago
- TLMu - Transaction Level eMulator☆36Updated 11 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 5 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆103Updated 4 years ago