andestech / riscv-llvm

Related projects ⓘ

Alternatives and complementary repositories for riscv-llvm

• felsabbagh3 / Vortex
  RISC-V GPGPU
  ☆34Updated 4 years ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆71Updated last year
• esperantotech / boom-template
  A template for building new projects/platforms using the BOOM core.
  ☆24Updated 5 years ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆57Updated last year
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆72Updated 5 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆153Updated 4 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 4 years ago
• tvanas / r-vex
  A reconfigurable and extensible VLIW processor implemented in VHDL
  ☆30Updated 9 years ago
• ucb-bar / sha3
  ☆76Updated 8 months ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆52Updated 4 years ago
• sifive / verilator
  Fork of Verilator with prebuilt Ubuntu binaries (https://www.veripool.org/wiki/verilator)
  ☆22Updated 2 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆19Updated this week
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆79Updated last month
• intel / rapid-design-methods-for-developing-hardware-accelerators
  ☆84Updated last year
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆135Updated last month
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆80Updated 3 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 2 years ago
• riscv / riscv-test-env
  ☆40Updated 5 months ago
• ucb-bar / hwacha-template
  Template for projects using the Hwacha data-parallel accelerator
  ☆34Updated 4 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆161Updated 3 months ago
• plctlab / plct-gem5
  upstream: https://github.com/RALC88/gem5
  ☆32Updated last year
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆92Updated 5 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆64Updated 4 years ago
• CTSRD-CHERI / SIMTight
  Synthesisable SIMT-style RISC-V GPGPU
  ☆28Updated last week
• riscvarchive / riscv-fesvr
  RISC-V Frontend Server
  ☆62Updated 5 years ago
• jbush001 / NyuziToolchain
  Port of LLVM/Clang C compiler to Nyuzi parallel processor architecture
  ☆62Updated last year
• sifive / fpga-shells
  ☆131Updated 2 years ago
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆85Updated last year
• VerticalResearchGroup / microbench
  Extremely Simple Microbenchmarks
  ☆30Updated 6 years ago
• riscv-admin / riscv-ovpsim
  ☆60Updated 3 years ago