rvboards / d1_demo
The demo projects for Allwinner D1 SBC
☆24Updated 3 years ago
Alternatives and similar repositories for d1_demo:
Users that are interested in d1_demo are comparing it to the libraries listed below
- YuzukiNezha D1s is a SOM based on Allwinner D1s☆15Updated 3 years ago
- Standalone SDK for kendryte K210☆24Updated 4 years ago
- The directory to save Bumblebee core's documents, just for GD32VF103 RISC-V Core☆41Updated 3 years ago
- A 32bit RISC-V SoC on FPGA (EG4S20) that supports RT-Thread.☆12Updated 4 years ago
- Embedded libc,especially for RISC-V.☆34Updated 3 weeks ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆26Updated last year
- sipeed2022_spring_competition☆11Updated 2 years ago
- ☆43Updated 3 years ago
- riscv64 d1-nezha baremeta(Allwinner D1 riscv chip)☆78Updated 3 years ago
- A Python-based cross-platform Kendryte K210 UART ISP Utility, enhanced kflash.py☆35Updated 4 years ago
- M1s(BL808)SDK☆57Updated last year
- TensorFlow Lite for BL602☆11Updated 3 years ago
- Allwinner document collection☆44Updated 4 months ago
- build mainline SBI and Linux for allwinner D1 nezha board☆10Updated 3 years ago
- Deprecated, no longer updated, please change to https://www.nucleisys.com/index.php☆25Updated 3 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆13Updated last year
- Deprecated, please use https://github.com/Nuclei-Software/nuclei-sdk☆20Updated 3 years ago
- 国产全志平头哥C906 RISC-V DongshanPI-D1s RV64GVC 裸机示例仓库!☆11Updated 9 months ago
- ☆25Updated 3 years ago
- GoAI 2.0 Public Repository☆22Updated 2 years ago
- Buildroot customized for Xuantie™ RISC-V CPU☆41Updated 3 years ago
- Reindeer Soft CPU for Step CYC10 FPGA board☆27Updated 4 years ago
- The directory to save GD32VF103 Demo_Suites☆33Updated 4 years ago
- RISC-V Architecture☆19Updated 2 years ago
- Yocto project for Xuantie RISC-V CPU☆38Updated last month
- Kendryte GNU Toolchain☆75Updated 5 years ago
- Allwinner D1 For RISCV-64 Boards Awesome.☆81Updated 2 years ago
- 蚂蚁S9矿板移植pynq2.5☆25Updated 4 years ago
- Share JTAG chain within RISCV core and Xilinx FPGA.☆9Updated 5 years ago
- Mainline-friendly SPL for D1☆34Updated 2 years ago