rvboards / d1_demoLinks
The demo projects for Allwinner D1 SBC
☆24Updated 3 years ago
Alternatives and similar repositories for d1_demo
Users that are interested in d1_demo are comparing it to the libraries listed below
Sorting:
- riscv64 d1-nezha baremeta(Allwinner D1 riscv chip)☆82Updated 3 years ago
- K210 run linux nommu (From Damien Le Moal's patch)☆158Updated 2 years ago
- M1s(BL808)SDK☆57Updated 2 years ago
- A baremetal experiment of Allwinner D1, without FEL☆33Updated 2 years ago
- Linux0.11 with MMU for K210(RISC-V) Version☆89Updated 5 years ago
- build mainline SBI and Linux for allwinner D1 nezha board☆10Updated 4 years ago
- Allwinner D1 For RISCV-64 Boards Awesome.☆82Updated 3 years ago
- Mainline-friendly SPL for D1☆34Updated 2 years ago
- Reverse engineering the V831 npu☆94Updated 4 years ago
- Deprecated, no longer updated, please change to https://www.nucleisys.com/index.php☆25Updated 4 years ago
- Buildroot customized for Xuantie™ RISC-V CPU☆46Updated 3 years ago
- TensorFlow Lite for BL602☆11Updated 4 years ago
- The directory to save Bumblebee core's documents, just for GD32VF103 RISC-V Core☆42Updated 4 years ago
- Share JTAG chain within RISCV core and Xilinx FPGA.☆9Updated 5 years ago
- Standalone SDK for kendryte K210☆23Updated 4 years ago
- ☆43Updated 4 years ago
- Embedded libc,especially for RISC-V.☆36Updated 2 weeks ago
- Deprecated, please use https://github.com/Nuclei-Software/nuclei-sdk☆21Updated 4 years ago
- sipeed2022_spring_competition☆11Updated 3 years ago
- Kendryte GNU Toolchain☆75Updated 6 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆28Updated last year
- Kendryte K230 SDK Docs☆114Updated 4 months ago
- ☆96Updated 3 years ago
- Kendryte K210 datasheet☆130Updated 5 years ago
- M1s_BL808_example☆70Updated 2 years ago
- ☆10Updated 4 years ago
- sipeed opensource mechanical keyboard make with BL706☆70Updated 3 years ago
- SyterKit is a baremetal framework, As bootloader, MPU framework, Running on SRAM☆121Updated 2 weeks ago
- This stream transmission protocol is used for data transmission between some fpgas.☆9Updated 3 years ago
- RISC-V Architecture☆22Updated 2 years ago