Alternatives and similar repositories for virtex-ultrascale-pcie

Users that are interested in virtex-ultrascale-pcie are comparing it to the libraries listed below

• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆50Updated 3 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆88Updated 4 years ago
• intel / fpga-partial-reconfig
  Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  ☆90Updated 10 months ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 7 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆69Updated 3 weeks ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated 2 months ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 6 years ago
• erinadreno / list_of_Xilinx_FPGAs
  ☆38Updated 6 months ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆63Updated last month
• FPGA-House-AG / BrightAI-Blackwire
  BrightAI B.V. open sources its Blackwire RTL FPGA smartNIC implementation of WireGuard
  ☆61Updated 2 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• antmicro / kintex-410t-devboard
  ☆38Updated last month
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 9 months ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆53Updated 2 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆151Updated last month
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• Avnet / petalinux
  Repository used to support automated builds under PetaLinux tools that use Yocto.
  ☆63Updated 9 months ago
• fpgadeveloper / ethernet-fmc-processorless
  Example designs for using Ethernet FMC without a processor (ie. state machine based)
  ☆34Updated last year
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆104Updated last year
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆52Updated 4 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 4 years ago
• zeeshanrafique23 / mdu
  M-extension for RISC-V cores.
  ☆32Updated last year
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆128Updated 7 months ago
• waviousllc / wav-lpddr-sw
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆22Updated 3 years ago
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 5 months ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆51Updated 10 years ago
• CESNET / ndk-fpga
  Network Development Kit (NDK) for FPGA cards with example application
  ☆68Updated this week
• tomtor / HDL-deflate
  FPGA implementation of deflate (de)compress RFC 1950/1951
  ☆63Updated 6 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆32Updated 3 years ago