antmicro / virtex-ultrascale-pcie
☆14Updated last year
Alternatives and similar repositories for virtex-ultrascale-pcie:
Users that are interested in virtex-ultrascale-pcie are comparing it to the libraries listed below
- Small footprint and configurable Inter-Chip communication cores☆54Updated last week
- Virtual development board for HDL design☆40Updated last year
- Bitstream relocation and manipulation tool.☆43Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆28Updated this week
- This repository contains sample code integrating Renode with Verilator☆19Updated last week
- This store contains Configurable Example Designs.☆44Updated 3 weeks ago
- Repository used to support automated builds under PetaLinux tools that use Yocto.☆58Updated 3 months ago
- End-to-End Open-Source I2C GPIO Expander☆29Updated 2 weeks ago
- FPGA reference design for the the Swerv EH1 Core☆69Updated 5 years ago
- FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.☆50Updated last month
- Extensible FPGA control platform☆55Updated last year
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- RISC-V Processor written in Amaranth HDL☆35Updated 2 years ago
- VexRiscv-SMP integration test with LiteX.☆25Updated 4 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- Open-source CSI-2 receiver for Xilinx UltraScale parts☆35Updated 5 years ago
- Python script for controlling the debug-jtag port of riscv cores☆14Updated 3 years ago
- Experimental breakout board for a signle 200-ball WFBGA LPDDR4 chip in SO-DIMM DDR4 form factor.☆13Updated 9 months ago
- CologneChip GateMate FPGA Module: GMM-7550☆20Updated 11 months ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆28Updated 3 weeks ago
- This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.☆41Updated 2 years ago
- Demo board for TT4 and beyond☆20Updated last week
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆24Updated 4 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆25Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated 3 weeks ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 5 years ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 8 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 6 months ago
- Reusable Verilog 2005 components for FPGA designs☆39Updated last year