ama142 / ZedboardOLED-v1.0-IP
☆16Updated this week
Related projects: ⓘ
- Demonstration of the AXI DMA engine on the ZedBoard☆50Updated 3 years ago
- ☆35Updated this week
- Example design for the Ethernet FMC using the hard GEMs of the Zynq☆52Updated 7 months ago
- Instructions and packages for Zybo compatibility to Pynq☆13Updated 5 years ago
- Demonstration of the AXI DMA engine on the MicroZed☆26Updated 3 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆62Updated 10 months ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆60Updated 7 years ago
- DMA enabled Zynq PS-PL communication to implement high throughput data transfer between Linux applications and user IP core.☆36Updated 7 years ago
- Ethernet MAC 10/100 Mbps☆75Updated 4 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 6 years ago
- Extensible FPGA control platform☆52Updated last year
- Fork of OpenCores jpegencode with Cocotb testbench☆42Updated 9 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆22Updated 5 years ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆92Updated 2 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- HDL and C source for WAVE Zynq Ultrascale+ SoC☆15Updated 2 years ago
- USB -> AXI Debug Bridge☆33Updated 3 years ago
- Revision Control Labs and Materials☆23Updated 6 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆40Updated 9 months ago
- IP Cores that can be used within Vivado☆24Updated 3 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆32Updated 6 years ago
- ☆18Updated 8 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆40Updated 4 years ago
- ☆79Updated 7 years ago
- Advanced Encryption Standard (AES) SystemVerilog Core