抢选课系统
☆22Sep 1, 2023Updated 2 years ago
Alternatives and similar repositories for project
Users that are interested in project are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆15Nov 12, 2025Updated 5 months ago
- 该文档是个人阅读学习蜂鸟E203源码的笔记☆13Aug 1, 2023Updated 2 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆13Aug 26, 2024Updated last year
- 基于易灵思Ti60F225开发板和MT9M001双目摄像头，使用Verilog语言完成的双目拼接项目。摄像头输入图像数据后，在使用FAST计算图像特征点的同时，构建滑动窗口计算图像各个像素点的BRIEF描述符，完成后根据BRIEF描述符对两幅图像上的特征点进行暴力匹配，最后…☆20Apr 16, 2025Updated last year
- 大三上做的本科毕设，包含BNN的替代梯度训练，verilog电路实现，完成180nm工艺流片。☆24Jun 30, 2025Updated 10 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- NTU Computer Architecture 2021 - CPU with Single issue, L1-cache☆11Jan 24, 2022Updated 4 years ago
- 深度学习笔记☆12Jul 31, 2018Updated 7 years ago
- 一个支持AXI总线、支持Cache、包括所有非浮点MIPS 1指令、支持例外的静态五级流水MIPS CPU☆11Oct 8, 2019Updated 6 years ago
- 《CPU设计实战》学习记录及代码☆14Dec 30, 2023Updated 2 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Dec 23, 2022Updated 3 years ago
- 基于Risc-V的计算机体系结构设计。一栈式打通riscv架构硬件模拟器、操作系统、应用层！☆21Nov 25, 2024Updated last year
- 计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab11~12 & 14~15☆22Dec 22, 2020Updated 5 years ago
- This project is AHB_SRAM design based on 启芯学堂,which contains all the source files.☆14Mar 13, 2022Updated 4 years ago
- ☆19May 1, 2023Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- 深度学习500问，以问答形式对常用的概率知识、线性代数、机器学习、深度学习、计算机视觉等热点问题进行阐述，以帮助自己及有需要的读者。 全书分为18个章节，50余万字。由于水平有限，书中不妥之处恳请广大读者批评指正。 未完待续............ 如有意合作，联系sc…☆13Oct 14, 2021Updated 4 years ago
- Write a CPU from scratch! (5-stage pipeline & 2-way-cache)☆21Jul 18, 2019Updated 6 years ago
- 基于Stemblock+shufflenet改进YOLOv5的垃圾分类检测系统☆29Nov 27, 2023Updated 2 years ago
- Violence detection using the latest yolo model version 8☆28Feb 16, 2024Updated 2 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Feb 6, 2024Updated 2 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.☆28Feb 11, 2024Updated 2 years ago
- ☆29Aug 2, 2022Updated 3 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 9 years ago
- 电梯调度仿真程序☆28Jan 9, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 广东工业大学教务系统选课助手☆29Mar 28, 2019Updated 7 years ago
- a public Infrared Ship Detection Dataset (ISDD)☆36Jun 13, 2022Updated 3 years ago
- 实现一个基础但功能完善的计算机系统,根据《自己动手写ＣＰＵ》实现，开发板为Nexys4 DDR☆34Mar 10, 2024Updated 2 years ago
- 仿牛客网社区开发☆28Jun 30, 2022Updated 3 years ago
- [CVPR 2025 🔥] MI-DETR: An Object Detection Model with Multi-time Inquiries Mechanism☆55Nov 1, 2025Updated 6 months ago
- 抢课用简易脚本，适用于华中科技大学/华科/华科网安/网络空间安全学院 Ez Script for HUST(Huazhong University of Science&Technology) OCSS☆34Sep 4, 2025Updated 8 months ago
- ☆40Mar 17, 2021Updated 5 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆57May 10, 2021Updated 5 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Feb 17, 2022Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- 基于改进YOLO的玉米病害识别系统（部署教程＆源码）☆56Dec 4, 2023Updated 2 years ago
- AXI Interconnect☆56Aug 20, 2021Updated 4 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 3 years ago
- 基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）☆53Apr 23, 2020Updated 6 years ago
- upgrade to e203 (a risc-v core)☆45Aug 9, 2020Updated 5 years ago
- 一个丰富的API开放调用平台，为开发者提供便捷、实用的API调用体验 Java + React 全栈项目，包括网站前台+管理员后台☆42Nov 14, 2023Updated 2 years ago
- Learning how to make RISC-V 32bit CPU with Chisel☆71Sep 17, 2021Updated 4 years ago