Alternatives and similar repositories for Advanced-Noise-Cancellation-System-for-Mobile-Communication-Using-Xilinx-Spartan-3E-FPGA-and-VHDL

Users that are interested in Advanced-Noise-Cancellation-System-for-Mobile-Communication-Using-Xilinx-Spartan-3E-FPGA-and-VHDL are comparing it to the libraries listed below

• ASP-SoC / ASP-SoC
  Audio Signal Processing SoC
  ☆18Updated 7 years ago
• amaranth-farm / usb2-highspeed-core
  a USB2 highspeed device core, written in amaranth HDL
  ☆49Updated 10 months ago
• kazkojima / pcm2pdm-example
  A tiny example of PCM to PDM pipeline on FPGA
  ☆21Updated 3 years ago
• pcsrule / zybo-audio
  Realtime audio DSP on the ZyBo
  ☆9Updated 9 years ago
• DaveBerkeley / fpga
  Verilog FPGA code : including experimental DSP audio processor
  ☆11Updated 4 years ago
• noscene / ice40_audio
  verilog example to drive PCM5102 DAC with FPGA
  ☆18Updated 7 years ago
• skristiansson / i2s
  i2s core, with support for both transmit and receive
  ☆31Updated 7 years ago
• controlpaths / cp_som_one
  Artix7 SOM
  ☆18Updated 10 months ago
• ultraembedded / core_audio
  Audio controller (I2S, SPDIF, DAC)
  ☆86Updated 5 years ago
• chili-chips-ba / uberClock
  Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numeric…
  ☆11Updated last week
• hukenovs / math
  Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)
  ☆30Updated 4 years ago
• kazkojima / lunauac2-pdm
  A LiteX module implementing a USB UAC2 module with simple PDM in/out
  ☆16Updated 3 years ago
• YetAnotherElectronicsChannel / FPGA-Class-D-Amplifier
  ☆65Updated 5 years ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆28Updated 5 years ago
• dwjbosman / I2S_sender
  VHDL I2S transmitter
  ☆13Updated 6 years ago
• YetAnotherElectronicsChannel / FPGA-Audio-IIR
  ☆24Updated 5 years ago
• michg / pyocdriscv32
  Python script for controlling the debug-jtag port of riscv cores
  ☆14Updated 4 years ago
• hamsternz / second_order_sigma_delta_DAC
  A comparison of 1st and 2nd order sigma delta DAC for FPGA
  ☆59Updated 4 years ago
• lambdaconcept / amaranth-to-litex
  Use amaranth-to-litex to simply import Amaranth code into a Litex project.
  ☆15Updated last year
• har-in-air / FPGA_STEREO_CROSSOVER
  Stereo digital 2-way crossover filters processing I2S audio (16bit or 24bit) streams
  ☆21Updated last year
• davemuscle / sigma_delta_converters
  Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components
  ☆71Updated 3 years ago
• har-in-air / SIPEED_TANG_PRIMER
  Projects using the Sipeed Tang Primer FPGA development board
  ☆14Updated 4 years ago
• controlpaths / blog
  Projects published on controlpaths.com and hackster.io
  ☆41Updated 3 years ago
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆94Updated 10 months ago
• dawsonjon / FPGA-radio
  Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC
  ☆109Updated 8 years ago
• m1geo / CIC-Filter
  A simple and crude CIC filter implementation in Python3 for learning purposes
  ☆22Updated 5 years ago
• tomverbeure / pdm
  ☆21Updated 4 years ago
• amoudgl / iir-bandstop-filter
  Implementation of pipelined IIR bandstop filter in Verilog, C++ and MATLAB with fixed point arithmetic
  ☆31Updated 8 years ago
• VHDPlus / VHDPlus_Libraries_and_Examples
  This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…
  ☆20Updated last year
• hydrausb3 / wch-ch569-serdes
  WCH CH569 SerDes Reverse Engineering
  ☆26Updated 2 years ago