Alternatives and similar repositories for viv-prj-gen

Users that are interested in viv-prj-gen are comparing it to the libraries listed below

• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated 2 weeks ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 6 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆70Updated 9 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆71Updated this week
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆53Updated last week
• OSVVM / Documentation
  OSVVM Documentation
  ☆34Updated this week
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆54Updated last week
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆44Updated 5 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆116Updated last month
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 4 months ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆58Updated 4 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆48Updated this week
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆64Updated this week
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆67Updated last week
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆54Updated last week
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆66Updated 6 months ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆36Updated last year
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆33Updated this week
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 6 years ago
• suoto / fpga_cores
  ☆32Updated 2 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆33Updated 4 months ago
• antmicro / verilator-verification-features-tests
  ☆24Updated this week
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆48Updated last year
• tsfpga / tsfpga
  A flexible and scalable development platform for modern FPGA projects.
  ☆29Updated this week
• SeanOBoyle / DoxygenFilterSystemVerilog
  ☆38Updated 10 years ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated 11 months ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆171Updated this week
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆138Updated last month