Alternatives and similar repositories for fixedpoint:

Users that are interested in fixedpoint are comparing it to the libraries listed below

• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated this week
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆81Updated 8 months ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• FPHDL / fphdl
  VHDL-2008 Support Library
  ☆57Updated 8 years ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆68Updated 3 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆55Updated last week
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 8 months ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆59Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆129Updated 2 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 6 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆60Updated 3 weeks ago
• SanDisk-Open-Source / pyvcd
  Python package for writing Value Change Dump (VCD) files.
  ☆115Updated 4 months ago
• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆73Updated 5 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆49Updated last week
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆114Updated last month
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆44Updated 4 years ago
• cirosantilli / vcdvcd
  Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
  ☆57Updated 4 months ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆68Updated 8 months ago
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆58Updated 2 weeks ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆47Updated this week
• Digilent / digilent-vivado-scripts
  ☆68Updated 2 weeks ago
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆76Updated 5 months ago
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆20Updated 4 years ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 6 years ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆64Updated 4 months ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated last month
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆62Updated 5 months ago