Alternatives and similar repositories for tinyfive

Users that are interested in tinyfive are comparing it to the libraries listed below

• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆44Updated 2 years ago
• litex-hub / linux-on-litex-rocket
  Run 64-bit Linux on LiteX + RocketChip
  ☆197Updated 9 months ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆146Updated 7 months ago
• regymm / buildroot
  buildroot fork from damien -- RV32 no MMU Linux. Run "make qemu_riscv32_nommu_virt_minimal_defconfig" then "make"
  ☆27Updated last year
• AntonLydike / riscemu
  RISC-V emulator in python
  ☆57Updated 10 months ago
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆84Updated 5 years ago
• popovicu / linux-no-mmu-userspace-example
  ☆41Updated last year
• mirimmad / riscv
  RISC-V(RV32IM) emulator with support for syscalls.
  ☆28Updated last year
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆71Updated this week
• AZHenley / riscv-parser
  Basis of a RISC-V parser to be used for linters or assemblers.
  ☆47Updated 3 years ago
• rtfb / riscv-hobby-os
  ☆29Updated 11 months ago
• mattvenn / wokwi-verilog-gds-test
  ☆55Updated 2 years ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆53Updated 6 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆93Updated 9 months ago
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆42Updated last year
• sellicott / tcc-riscv32
  Port TCC (Tiny C Compiler) to support Risc-V 32 targets (specifically for the ESP32-C3). This project is a work-in-progress and is not cu…
  ☆69Updated this week
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆136Updated 2 years ago
• riscvarchive / riscv-zicond
  The ISA specification for the ZiCondOps extension.
  ☆19Updated last year
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆108Updated last week
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆57Updated last year
• machdyne / kuchen
  Kuchen Computer
  ☆23Updated 11 months ago
• antoniocgj / RISC-V-ALE
  RISC-V Assembly Learning Environment
  ☆22Updated 8 months ago
• P3109 / Public
  materials available to the public
  ☆25Updated 6 months ago
• JulianKemmerer / PipelineC-Graphics
  Graphics demos
  ☆110Updated last year
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆165Updated 4 months ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated last month
• theandrew168 / bronzebeard
  Minimal assembler and ecosystem for bare-metal RISC-V development
  ☆50Updated last year
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆143Updated last week
• cucapra / filament
  Fearless hardware design
  ☆176Updated last month
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆60Updated last year