Alternatives and similar repositories for my-discrete-fpga

Users that are interested in my-discrete-fpga are comparing it to the libraries listed below

• howerj / bit-serial
  A bit-serial CPU written in VHDL, with a simulator written in C.
  ☆127Updated 10 months ago
• howerj / lfsr-vhdl
  An implementation of a CPU that uses a Linear Feedback Shift Register as a Program Counter instead of a normal one
  ☆52Updated last month
• fischermoseley / manta
  A configurable and approachable tool for FPGA debugging and rapid prototyping.
  ☆138Updated 3 months ago
• TinyTapeout / vga-playground
  Playground for VGA projects on Tiny Tapeout
  ☆63Updated 4 months ago
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆86Updated 5 years ago
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆219Updated last year
• suarezvictor / litex_imgui_usb_demo
  Soft USB for LiteX
  ☆50Updated 2 years ago
• TinyTapeout / siliwiz
  Silicon Layout Wizard
  ☆172Updated last month
• Forty-Bot / ethernet
  WIP 100BASE-TX PHY
  ☆76Updated 7 months ago
• lawrie / fpga_pio
  An attempt to recreate the RP2040 PIO in an FPGA
  ☆301Updated last year
• regymm / pcie_7x
  PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
  ☆45Updated 2 months ago
• smunaut / doom_riscv
  Doom classic port to lightweight RISC‑V
  ☆94Updated 2 years ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated last week
• suarezvictor / CflexHDL
  Design digital circuits in C. Simulate really fast with a regular compiler.
  ☆174Updated 2 years ago
• orangecrab-fpga / orangecrab-examples
  Example projects/code for the OrangeCrab
  ☆106Updated last year
• siliconcompiler / logik
  A configurable RTL to bitstream FPGA toolchain
  ☆35Updated 2 weeks ago
• ulx3s / fpga-odysseus
  FPGA Odysseus with ULX3S
  ☆66Updated last year
• gregdavill / ecpprog
  Programmer for the Lattice ECP5 series, making use of FTDI based adaptors
  ☆91Updated 8 months ago
• olofk / vidbo
  Virtual Development Board
  ☆60Updated 3 years ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆178Updated last month
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆95Updated last month
• olofk / corescore
  CoreScore
  ☆157Updated 5 months ago
• cpldcpu / PCBFlow
  VHDL to Discrete Logic on PCB Flow
  ☆122Updated 6 months ago
• bl0x / learn-fpga-amaranth
  Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
  ☆107Updated 11 months ago
• oskirby / logicbone
  Logicbone ECP5 Development Board
  ☆117Updated 5 years ago
• RadionaOrg / ulx3s-links
  List of all links you can try with ULX3S
  ☆100Updated 3 years ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 2 months ago
• turbo9team / turbo9
  Turbo9 - Pipelined 6809 Microprocessor IP
  ☆159Updated 9 months ago
• f4pga / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆56Updated 2 years ago
• smunaut / iCE40linux
  Gateware / Firmware / BuildRoot to run linux on iCE40 / iCEBreaker
  ☆100Updated 2 years ago