Alternatives and similar repositories for RISC-V-ALE

Users that are interested in RISC-V-ALE are comparing it to the libraries listed below

• j-core / jcore-cpu
  J-Core J2/J32 5 stage pipeline CPU core
  ☆53Updated 4 years ago
• Wren6991 / NorForkConditionally
  What's the simplest CPU you can build?
  ☆35Updated 11 years ago
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆72Updated this week
• jowinter / dmacu
  Minimal CPU Emulator Powered by the ARM PL080 DMA Controller
  ☆36Updated last year
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆86Updated 5 years ago
• ghaerr / blink16
  Tiny visual 8086 emulator based on Blink
  ☆75Updated last year
• IdanHo / RISCVEmu
  A Basic C++ RISC-V Emulator
  ☆18Updated 4 years ago
• sylefeb / Iron
  Iron: selectively turn RISC-V binaries into hardware
  ☆23Updated 2 years ago
• machdyne / kakao
  Kakao Linux
  ☆37Updated 3 months ago
• j-core / jcore-soc
  J-Core SoC Base Platfrom. Top level for FPGA platforms, pulls in CPU, BootROM and various IP blocks.
  ☆24Updated 4 years ago
• jhhuh / tinyemu
  Fabrice Bellard's tinyemu (https://bellard.org/tinyemu/)
  ☆65Updated 3 years ago
• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆45Updated 3 years ago
• howerj / lfsr-vhdl
  An implementation of a CPU that uses a Linear Feedback Shift Register as a Program Counter instead of a normal one
  ☆52Updated 3 months ago
• sellicott / tcc-riscv32
  Port TCC (Tiny C Compiler) to support Risc-V 32 targets (specifically for the ESP32-C3). This project is a work-in-progress and is not cu…
  ☆72Updated this week
• classilla / 6o6
  Why can't the 6502 virtualize itself? Good question.
  ☆18Updated last year
• noteed / riscv-hello-asm
  Bare metal RISC-V assembly hello world
  ☆60Updated 3 years ago
• suarezvictor / litex_imgui_usb_demo
  Soft USB for LiteX
  ☆50Updated 2 years ago
• defparam / higan-verilog
  This is a higan/Verilator co-simulation example/framework
  ☆51Updated 7 years ago
• revaldinho / opc
  One Page CPU Project - CPU, Assembler & Emulator each in a single page of code
  ☆82Updated last year
• popovicu / linux-no-mmu-userspace-example
  ☆42Updated last year
• devzendo / transputer-emulator
  This is a portable, open source emulator of the 32-bit Inmos T414/T800/T801/T805 Transputer family, and a host/file I/O Server that inter…
  ☆20Updated 2 weeks ago
• markablov / i40xx
  Javascript emulator for intel 4004/4040
  ☆18Updated 9 months ago
• mikeakohn / w65c832
  W65C832 (32 bit 6502) in an FPGA.
  ☆57Updated 2 weeks ago
• howerj / bit-serial
  A bit-serial CPU written in VHDL, with a simulator written in C.
  ☆129Updated last year
• krakenlake / vmon
  Tiny RISC-V machine code monitor written in RISC-V assembly.
  ☆53Updated last month
• clausecker / palanqin
  ARM Cortex M0 emulator for DOS
  ☆29Updated last year
• shrine-maiden-heavy-industries / torii-hdl
  A Python-based HDL and framework for silicon-based witchcraft
  ☆25Updated this week
• gateware-ts / gateware-ts
  Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools
  ☆104Updated 2 years ago
• betrusted-io / betrusted-ec
  Betrusted embedded controller (UP5K)
  ☆48Updated last year
• theandrew168 / bronzebeard
  Minimal assembler and ecosystem for bare-metal RISC-V development
  ☆53Updated last year