Alternatives and similar repositories for awesome-compilers

Users that are interested in awesome-compilers are comparing it to the libraries listed below

• xmpf / awesome-risc-v
  Curated list of awesome resources related with RISC-V
  ☆94Updated 3 years ago
• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆46Updated 8 years ago
• merledu / nucleusrv
  NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
  ☆76Updated last month
• Jonathan2251 / lbt
  Develop toolchain based on llvm to for Cpu0 processor
  ☆52Updated last month
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• hadibrais / archsim
  A survey on architectural simulators focused on CPU caches.
  ☆16Updated 5 years ago
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated 2 years ago
• ychen306 / vegen
  ☆31Updated 3 years ago
• emanueledelsozzo / awesome-fpga-programming
  An awesome curated list of languages and tools to program FPGAs
  ☆72Updated 3 years ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆162Updated 3 years ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆150Updated 2 years ago
• quepas / Compiler-benchmark-suites
  A list of benchmark suites used in the research related to compilers, program performance, scientific computations etc.
  ☆59Updated 2 years ago
• rachelselinar / ReGDS-Logic-Gate-Extraction
  A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog …
  ☆31Updated last year
• open64-compiler / open64
  open64 compiler
  ☆89Updated 2 years ago
• leros-dev / leros
  A Tiny Processor Core
  ☆114Updated 5 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆168Updated 5 years ago
• plctlab / riscv-vectorized-benchmark-suite
  RISC-V Vectorized Bencmark Suite. based on https://github.com/RALC88/riscv-vectorized-benchmark-suite
  ☆12Updated 3 years ago
• michaeljclark / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆101Updated 3 years ago
• mc-imperial / multicore-test-harness
  A multicore microprocessor test harness for measuring interference
  ☆14Updated 5 years ago
• openhwgroup / corev-llvm-project
  ☆18Updated last year
• zslwyuan / LLVM-9.0-Learner-Tutorial
  A blog for LLVM(v9.0.0 or v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM and accompli…
  ☆105Updated 3 years ago
• riscvarchive / riscv-code-size-reduction
  ☆147Updated last year
• rhysd / riscv32-cpu-chisel
  Learning how to make RISC-V 32bit CPU with Chisel
  ☆70Updated 4 years ago
• makslevental / mmlir
  A minimal (really) out-of-tree MLIR example
  ☆46Updated 4 months ago
• mshockwave / SQLGen
  Generate SQL from TableGen code - This is part of the tutorial "How to write a TableGen backend" in 2021 LLVM Developers' Meeting.
  ☆34Updated 2 years ago
• nfinit / ansibench
  A selection of ANSI C benchmarks and programs useful as benchmarks
  ☆97Updated last year
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆32Updated 4 years ago
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆137Updated 3 weeks ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆88Updated last year
• AntonLydike / riscemu
  RISC-V emulator in python
  ☆62Updated last year