Alternatives and similar repositories for awesome-compilers

Users that are interested in awesome-compilers are comparing it to the libraries listed below

• xmpf / awesome-risc-v
  Curated list of awesome resources related with RISC-V
  ☆94Updated 3 years ago
• merledu / nucleusrv
  NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
  ☆76Updated last month
• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆47Updated 8 years ago
• larkmjc / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆101Updated 3 years ago
• leros-dev / leros
  A Tiny Processor Core
  ☆114Updated 5 months ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• cdkersey / chdl
  A C++ Hardware Description Language and Toolchain
  ☆23Updated 2 years ago
• grigory-rechistov / simbook
  Simulation Foundations Book, in Russian
  ☆15Updated last month
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆162Updated 3 years ago
• AaronNGray / CompilerDesignInC
  Allen Holub's Book 'Compiler Design In C' source code
  ☆39Updated 9 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆108Updated 4 years ago
• mausimus / rvcc
  Standalone C compiler for RISC-V and ARM
  ☆97Updated last year
• hadibrais / archsim
  A survey on architectural simulators focused on CPU caches.
  ☆16Updated 5 years ago
• Jonathan2251 / lbt
  Develop toolchain based on llvm to for Cpu0 processor
  ☆52Updated 2 months ago
• AntonLydike / riscemu
  RISC-V emulator in python
  ☆63Updated last year
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆169Updated 5 years ago
• RohanNagar / parallel-logic-networks
  Gate-Level Simulation on a GPU
  ☆10Updated 9 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.
  ☆38Updated last week
• hughperkins / cpu-tutorial
  Tutorial on building your own CPU, in Verilog
  ☆35Updated 3 years ago
• makslevental / mmlir
  A minimal (really) out-of-tree MLIR example
  ☆46Updated 4 months ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆42Updated 7 years ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆89Updated last year
• HEAPLab / TAFFO
  Tuning Assistant for Floating point to Fixed point Optimization
  ☆19Updated 3 years ago
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated 2 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆152Updated last month
• merledu / SIngle-Cycle-RISC-V-In-Verilog
  This repository contains the verilog code files of Single Cycle RISC-V architecture
  ☆39Updated 6 years ago
• openhwgroup / corev-llvm-project
  ☆18Updated last year
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆39Updated 4 months ago
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆50Updated last year
• alirezakay / RISC-CPU
  A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
  ☆29Updated 4 years ago