Alternatives and similar repositories for awesome-compilers:

Users that are interested in awesome-compilers are comparing it to the libraries listed below

• llvm / eudsl
  Embedded Universal DSL: a good DSL for us, by us
  ☆32Updated this week
• makslevental / mmlir
  A minimal (really) out-of-tree MLIR example
  ☆43Updated 2 weeks ago
• AaronNGray / CompilerDesignInC
  Allen Holub's Book 'Compiler Design In C' source code
  ☆38Updated 9 years ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆31Updated last week
• orodley / naive
  Self-hosting C toolchain, from scratch
  ☆34Updated last month
• jvstech / float-compare-pass
  Fork of LLVM for demonstrating optimization pass development
  ☆31Updated 2 years ago
• GPUOpen-Drivers / llvm-dialects
  LLVM Dialects Library
  ☆22Updated last week
• iree-org / iree-bare-metal-arm
  Example for running IREE in a bare-metal Arm environment.
  ☆33Updated 3 weeks ago
• compiler-explorer / compiler-workflows
  Workflows to build daily and ad hoc compilers for Compiler Explorer
  ☆18Updated last month
• MPACT-ORG / mpact-compiler
  Retargetable ML compilers for the twenty-first century!
  ☆12Updated this week
• P3109 / Public
  materials available to the public
  ☆24Updated 4 months ago
• jserv / jit-construct
  JIT compiler from scratch, derived from Nick Desaulniers' great work
  ☆43Updated 4 years ago
• lmcad-unicamp / riscv-sbt
  RISC-V Static Binary Translator
  ☆17Updated 6 years ago
• grigory-rechistov / simbook
  Simulation Foundations Book, in Russian
  ☆13Updated last year
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆41Updated 11 months ago
• noteed / riscv-hello-c
  Bare metal RISC-V hello world in C
  ☆19Updated 5 years ago
• bit-hack / riscv-vm
  A Small RISC-V Virtual Machine
  ☆77Updated 3 years ago
• lifting-bits / gap
  A utility library to bridge llvm and mlir gaps.
  ☆13Updated 2 months ago
• Jonathan2251 / lbt
  Develop toolchain based on llvm to for Cpu0 processor
  ☆45Updated last year
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆30Updated last week
• OpenMachine-ai / tinyfive
  TinyFive is a lightweight RISC-V emulator and assembler written in Python with neural network examples
  ☆56Updated last year
• synogate / gatery
  Gatery, a library for circuit design.
  ☆19Updated 3 months ago
• klessydra / T13x
  An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …
  ☆47Updated 7 months ago
• Lichtso / riscv-llvm-templates
  Code templates to get started experimenting with the RISC-V LLVM toolchain
  ☆13Updated 6 years ago
• DoctorWkt / fbcc
  Fabrice Bellard's fbcc C Compiler
  ☆41Updated 5 years ago
• xmpf / awesome-risc-v
  Curated list of awesome resources related with RISC-V
  ☆72Updated 2 years ago
• wpmed92 / shaderpulse
  A GLSL compiler targeting SPIR-V mlir
  ☆18Updated 5 months ago
• michalpaszkowski / LLVM-Canon
  LLVM-Canon aims to transform LLVM modules into a canonical form by reordering and renaming instructions while preserving the same semanti…
  ☆14Updated 10 months ago
• ychen306 / vegen
  ☆28Updated 2 years ago
• ManyThreads / mythos
  Many Threads Operating System
  ☆18Updated 2 years ago