Alternatives and similar repositories for awesome-compilers

Users that are interested in awesome-compilers are comparing it to the libraries listed below

• xmpf / awesome-risc-v
  Curated list of awesome resources related with RISC-V
  ☆89Updated 3 years ago
• emanueledelsozzo / awesome-fpga-programming
  An awesome curated list of languages and tools to program FPGAs
  ☆67Updated 3 years ago
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated 2 years ago
• merledu / nucleusrv
  NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
  ☆75Updated 3 weeks ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆159Updated 3 years ago
• opencompl / mlir-fuzz
  A enumerator for MLIR, relying on the information given by IRDL.
  ☆18Updated last week
• llvm / eudsl
  Embedded Universal DSL: a good DSL for us, by us
  ☆48Updated this week
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆38Updated 2 months ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆31Updated 4 years ago
• splinedrive / lets_build_a_compiler_for_riscv
  A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw
  ☆117Updated 3 years ago
• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆43Updated 8 years ago
• hadibrais / archsim
  A survey on architectural simulators focused on CPU caches.
  ☆16Updated 5 years ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆151Updated 2 years ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆42Updated 7 years ago
• zslwyuan / LLVM-9.0-Learner-Tutorial
  A blog for LLVM(v9.0.0 or v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM and accompli…
  ☆104Updated 3 years ago
• sabbaghm / c-ll-verilog
  An LLVM based mini-C to Verilog High-level Synthesis tool
  ☆39Updated 7 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆164Updated 5 years ago
• Jonathan2251 / lbt
  Develop toolchain based on llvm to for Cpu0 processor
  ☆49Updated 2 weeks ago
• michaeljclark / riscv-disassembler
  RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC
  ☆101Updated 3 years ago
• riscv-admin / riscv-ovpsim
  ☆61Updated 4 years ago
• VerticalResearchGroup / microbench
  Extremely Simple Microbenchmarks
  ☆36Updated 7 years ago
• openhwgroup / corev-llvm-project
  ☆17Updated last year
• leros-dev / leros
  A Tiny Processor Core
  ☆113Updated 3 months ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆148Updated 2 months ago
• iree-org / iree-bare-metal-arm
  Example for running IREE in a bare-metal Arm environment.
  ☆40Updated 2 months ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆34Updated this week
• hughperkins / cpu-tutorial
  Tutorial on building your own CPU, in Verilog
  ☆35Updated 3 years ago
• agra-uni-bremen / symex-vp
  A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
  ☆26Updated 2 years ago
• comsec-group / encarsia
  ☆24Updated 6 months ago
• fmash16 / riscv_emulator
  A basic working RISCV emulator written in C
  ☆73Updated last year