Fedex100 / awesome-compilersLinks
☆18Updated 8 years ago
Alternatives and similar repositories for awesome-compilers
Users that are interested in awesome-compilers are comparing it to the libraries listed below
Sorting:
- Curated list of awesome resources related with RISC-V☆94Updated 3 years ago
- Simple demonstration of using the RISC-V Vector extension☆50Updated last year
- A survey on architectural simulators focused on CPU caches.☆16Updated 6 years ago
- NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.☆77Updated 3 weeks ago
- An awesome curated list of languages and tools to program FPGAs☆73Updated 3 years ago
- Develop toolchain based on llvm to for Cpu0 processor☆53Updated 3 months ago
- A blog for LLVM(v9.0.0 or v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM and accompli…☆105Updated 3 years ago
- LLVM (Low Level Virtual Machine) Guide. Learn all about the compiler infrastructure, which is designed for compile-time, link-time, run-t…☆192Updated 2 years ago
- C++17 implementation of an AST for Verilog code generation☆24Updated 2 years ago
- A powerful and modern open-source architecture description language.☆49Updated 8 years ago
- Tutorial on building a gpu compiler backend in LLVM☆54Updated last year
- A teaching-focused RISC-V CPU design used at UC Davis☆154Updated 3 years ago
- RISC-V Disassembler with support for RV32/RV64/RV128 IMAFDC☆101Updated 3 years ago
- ☆62Updated 5 years ago
- ☆31Updated 3 years ago
- open64 compiler☆91Updated 2 years ago
- Embedded Universal DSL: a good DSL for us, by us☆66Updated this week
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆143Updated 2 weeks ago
- Lightweight and performant dynamic binary translation for RISC–V code on x86–64☆61Updated 4 years ago
- A minimal (really) out-of-tree MLIR example☆46Updated 5 months ago
- Extremely Simple Microbenchmarks☆39Updated 7 years ago
- ☆18Updated last year
- RISC-V emulator in python☆63Updated last year
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆38Updated last week
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆27Updated 2 years ago
- Example for running IREE in a bare-metal Arm environment.☆40Updated 6 months ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆31Updated 4 years ago
- A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )☆29Updated 4 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆162Updated 3 years ago
- An ARMv8 virtual platform based on QEMU and VCML☆47Updated this week